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600 mhz dual integrated dcl with ppmu, vhh drive capability, level setting dacs, and on-chip calibration engine adate318 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 600 mhz/1200 mbps data rate 3-level driver with high-z and reflection clamps window and differential comparators 25 ma active load per pin ppmu with ?2.0 v to +6.5 v range low leakage mode (typically 4 na) integrated 16-bit dacs with offset and gain correction high speed operating voltage range: C1.5 v to + 6.5 v dedicated vhh output pin range: 0.0 v to 13.5 v 1.1 w power dissipation per channel driver 3-level voltage range: C1.5 v to + 6.5 v precision trimmed output resistance unterminated swing: 200 mv minimum to 8 v maximum 725 ps minimum pulse width, vih ? vil = 2.0 v comparator differential and single-ended window modes >1.2 ghz input equivalent bandwidth load 25 ma current range per pin ppmu (ppmu) force voltage/compliance range: C2.0 v to +6.5 v 5 current ranges: 40 ma, 1 ma, 100 a, 10 a, 2 a external sense input for system pmu go/no-go comparators levels fully integrated 16-bit dacs on-chip gain and offset calibration registers and add/multiply engine package 84-lead 10 mm 10 mm lfcsp (0.4 mm pitch) applications automatic test equipment semiconductor test systems board test systems instrumentation and characterization equipment general description the adate318 is a complete, single-chip ate solution that performs the pin electronics functions of driver, comparator, and active load (dcl), four quadrant, per pin, parametric measurement unit (ppmu). it has vhh drive capability per chip to support flash memory testing applications and integ- rated 16-bit dacs with an on-chip calibration engine to provide all necessary dc levels for operation of the part. the driver features three active states: data high, data low, and terminate mode, as well as a high impedance inhibit state. the inhibit state, in conjunction with the integrated dynamic clamps, facilitates the implementation of a high speed active termination. the output voltage capability is ?1.5 v to +6.5 v to accommodate a wide range of ate and instrumentation applications. the adate318 can be used as a dual, single-ended drive/ receive channel or as a single differential drive/receive channel. each channel of the adate318 features a high speed window comparator as well as a programmable threshold differential comparator for differential ate applications. a four quadrant ppmu is also provided per channel. all dc levels for dcl and ppmu functions are generated by 24 on-chip 16-bit dacs. to facilitate accurate levels programming, the adate318 contains an integrated calibration function to correct gain and offset errors for each functional block. correction coefficients can be stored on chip, and any values written to the dacs are automatically adjusted using the appropriate correction factors. the adate318 uses a serial programmable interface (spi) bus to program all functional blocks, dacs, and on-chip calibration constants. it also has an on-chip temperature sensor and over/undervoltage fault clamps for monitoring and reporting the device temperature and any output pin or ppmu voltage faults that may occur during operation.
adate318 rev. 0 | page 2 of 80 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications..................................................................................... 4 ? spi timing details ..................................................................... 22 ? absolute maximum ratings.......................................................... 27 ? thermal resistance .................................................................... 27 ? esd caution................................................................................ 27 ? pin configuration and function descriptions........................... 28 ? typical performance characteristics ........................................... 31 ? spi interconnect details ................................................................ 49 ? use of the spi busy pin................................................................ 50 ? reset sequence and the rst pin .................................................. 51 ? spi register definitions and memory map................................ 52 ? control register details................................................................. 55 ? level setting dacs......................................................................... 63 ? dac update modes ................................................................... 63 ? dac transfer functions ........................................................... 67 ? gain and offset correction ...................................................... 68 ? x 2 registers.................................................................................. 68 ? sample calculations of m and c ............................................... 68 ? power supply, grounding, and decoupling strategy ................ 70 ? user information and truth tables ............................................. 71 ? alarm functions......................................................................... 72 ? ppmu external capacitors....................................................... 72 ? temperature sensor ................................................................... 72 ? default test conditions............................................................. 73 ? detailed functional block diagrams........................................... 74 ? outline dimensions ....................................................................... 80 ? ordering guide .......................................................................... 80 ? revision history 4/11revision 0: initial version
adate318 rev. 0 | page 3 of 80 functional block diagram ovdh ovdl to alarm (high/low voltage fault) over- voltage voh 0 vol 0 ppmu go/no-go therm to alarm (ppmu high/low clamp fault) out ppmu adate318 s f ppmu_vin0 vch0 vcl0 vch0 vcl0 vcom 0 100? 100 ? 50 ? 50? ioh0 vih0 vit/vcom0 vil0 mux mux driver 50? active load + ? voh0 vol0 nwc nwc diff ch0 only comparator dat 0 rcv 0 common channel 0 channel 1 (same as channel 0 except where noted) vhh driver vhh vih0 vil0 mux 2 12 16-bit dacs gain/offset correction alarm temp sensor spi pmu_s0 dut0 hvout vplus vdd vcc pgnd dgnd vss rst busy sdo cs sclk sdi alarm therm cmpl0 cmpl0 cmph0 cmph0 vttc0 rcv0 rcv0 dat0 dat0 ppmu_s0 ppmu_meas0 ppmu_cmpl0 ppmu_cmph0 09530-001 iol0 figure 1.
adate318 rev. 0 | page 4 of 80 specifications vdd = +10.0 v, vcc = +2.5 v, vss = ? 6.0 v, vplus = +16.75 v, vttcx = +1.2 v, vref = 5.000 v, vrefgnd = 0.000 v. all test conditions are as defined in table 32 . all specified values are at t j = 50c, where t j corresponds to the internal temperature sensor reading (therm pin), unless otherwise noted. temperature coefficients are measured around t j = 50 20c, unless otherwise noted. typical values are based on statistical mean of design, simulation analyses, and/or limited bench evaluation data. typical valu es are neither tested nor guaranteed. see table 16 for an explanation of test levels. table 1. detailed electrical specifications parameter min typ max unit test level conditions total function output leakage current, dcl disable ppmu range e ?10.0 4.0 +10.0 na p ?2.0 v < vdutx < +6.5 v, ppmu and dcl disabled, ppmu range e, vcl = ?2.5 v, vch = +7.5 v ppmu range a, range b, range c, and range d 4.0 na c t ?2.0 v < vdutx < + 6.5 v, ppmu and dcl disabled, ppmu range a, range b, range c, range d, vcl = ?2.5 v, vch = + 7.5 v output leakage current, driver high-z mode ?2 +2 a p ?2.0 v < vdutx < +7.0 v, ppmu disabled and dcl enabled, rcvx active, vcl = ?2.5 v, vch = +7.5 v dutx pin capacitance 1.2 pf s drive vit = 0.0 v dutx pin voltage range ?2.0 +7.0 v d power supplies total supply range, vplus to vss 22.75 23.55 v d vplus supply, vplus 15.90 16.75 17.60 v d defines dc psr conditions positive supply, vdd 9.5 10.0 10.5 v d defines dc psr conditions negative supply, vss ?6.3 ?6.0 ?5 .7 v d defines dc psr conditions logic supply, vcc 2.3 2.5 3.5 v d defines dc psr conditions comparator output termination, vttcx 0.5 1.2 3.3 v d vplus supply current, vplus 1.1 2.5 ma p vhh pin disabled 4.75 13.28 16.25 ma p vhh pin enabled, rcvx active, no load, vhh programmed level = 13.0 v logic supply current, vcc ?125 1 +125 a p quiescent (spi is static); vcc = 2.5 v 7.5 ma s current drawn during clocked portion of device reset sequence termination supply current, vttcx 30 45 50 ma p positive supply current, vdd 90 99 115 ma p load power-down (ioh = iol = 0 ma) negative supply current, vss 155 172 185 ma p load power-down (ioh = iol = 0 ma) total power dissipation 1.9 2.1 2.3 w p load power-down (ioh = iol = 0 ma) positive supply current, vdd 145 174 210 ma p load active off (ioh = iol = 25 ma) negative supply current, vss 210 246 280 ma p load active off (ioh = iol = 25 ma) total power dissipation 3.0 3.3 3.6 w p load active off (ioh = iol = 25 ma) positive supply current, vdd 167 ma c t load active off (ioh = iol = 25 ma), calibrated negative supply current, vss 238 ma c t load active off (ioh = iol = 25 ma), calibrated total power dissipation 3.2 w c t load active off (ioh = iol = 25 ma), calibrated positive supply current, vdd 109 ma c t load power-down, ppmu standby negative supply current, vss 183 ma c t load power-down, ppmu standby total power dissipation 2.3 w c t load power-down, ppmu standby
adate318 rev. 0 | page 5 of 80 parameter min typ max unit test level conditions temperature monitor temperature sensor gain 10 mv/k d temperature sensor accuracy over temperature range 6 k c t vref input reference dac reference input voltage range (vref pin) 4.950 5.000 5.050 v d provided externally: vref pin = +5.000 v vrefgnd pin = 0.000 v (not referenced to v dutgnd ) input bias current 100 a p tested with 5.000 v applied dutgnd input input voltage range, referenced to agnd ?0.1 + 0.1 v d input bias current ?100 +100 a p tested at ?100 mv and + 100 mv table 2. driver (vih ? vil 100 mv to me et dc and ac performance specifications) parameter min typ max unit test level conditions dc specifications high-speed differential input characteristics high speed input termination resistance: datx, rcvx 92 100 108 p impedance between each pair of datx and rcvx pins; push 4 ma into positive pin, force 0.8 v on negative pin, measure voltage between pins; calculate resistance ( v/ i) input voltage differential: datx, rcvx 0.2 0.4 1.0 v d 0.2 v < v dm < 1.0 v input voltage range: datx, rcvx 0.0 3.3 v d 0.0 v < (v cm v dm /2) < 3.3 v output characteristics output high range, vih ?1.4 +6.5 v d output low range, vil ?1.5 +6.4 v d output term range, vit ?1.5 +6.5 v d functional amplitude (vih C vil) 0.0 8.0 v d dc output current limit source 75 130 ma p drive high, vih = + 6.5 v, short dutx pin to ? 1.5 v, measure current dc output current limit sink ?130 ?75 ma p drive low, vil = ? 1.5 v, short dutx pin to + 6.5 v, measure current output resistance, 40 ma 46 48.6 51 p vdut/ idut; source: vih = 3.0 v, idut = + 1 ma, + 40 ma; sink: vil = 0.0 v, idut = ? 1 ma, ? 40 ma dc accuracy vih tests with vil = ? 2.5 v, vit = ? 2.5 v vil tests with vih = + 7.5 v, vit = + 7.5 v vit tests with vil = ? 2.5 v, vih = + 7.5 v, unless otherwise specified vih, vil, vit offset error ?500 +500 mv p me asured at dac code 0x4000 (0 v), uncalibrated vih, vil, vit offset tempco 625 v/c c t vih, vil, vit gain 1.0 1.1 v/v p gain deri ved from measurements at dac code 0x4000 (0 v) and dac code 0xc000 (5 v); based on ideal dac transfer functions (see table 21 ) vih, vil, vit gain tempco 40 ppm/c c t vih, vil, vit dnl 1 mv c t after two point gain/offset calibration; calibration points at 0x4000 (0 v) output; 0xc000 (+5 v) output; measured over full specified output range vih, vil, vit inl ?7 +7 mv p after two point gain/offset calibration; applies to nominal vdd = + 10.0 v supply case only
adate318 rev. 0 | page 6 of 80 parameter min typ max unit test level conditions vih, vil, vit resolution 153 v d dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range; measured at end points of vih, vil, and vit functional range dc levels interaction dc interaction on vil, vih, and vit output level while other driver dac levels are varied vih vs. vil 0.2 mv c t monitor interaction on vih = +6.5 v; sweep vil = ?1.5 v to +6.4 v, vit = +1.0 v vih vs. vit 1 mv c t monitor interaction on vih = +6.5 v; sweep vit = ?1.5 v to +6.5 v, vil = 0.0 v vil vs. vih 0.2 mv c t monitor interaction on vil = ?1.5 v; sweep vih = ?1.4 v to +6.5 v, vit = +1.0 v vil vs. vit 1 mv c t monitor interaction on vil = ?1.5 v; sweep vit = ?1.5 v to +6.5 v, vih = +2.0 v vit vs. vih 1 mv c t monitor interaction on vit = +1.0 v; sweep vih = ?1.4 v to +6.5 v, vil = ?1.5 v vit vs. vil 1 mv c t monitor interaction on vit = +1.0 v; sweep vil = ?1.5 v to +6.4 v, vih = +6.5 v overall voltage accuracy 8 mv c t vih ? vil 100 mv; sum of inl, dc interaction, dutgnd, and tempco errors over 5oc, after calibration vih, vil, vit dc psrr 10 mv/v c t measured at calibration points ac specifications all ac spec ifications performed after calibration rise/fall times toggle datx 0.2 v programmed swing, t rise 215 ps c b 20% to 80%, vih = 0.2 v, vil = 0.0 v, terminated 0.2 v programmed swing, t fall 277 ps c b 20% to 80%, vih = 0.2 v, vil = 0.0 v, terminated 0.5 v programmed swing, t rise 218 ps c b 20% to 80%, vih = 0.5 v, vil = 0.0 v, terminated 0.5 v programmed swing, t fall 274 ps c b 20% to 80%, vih = 0.5 v, vil = 0.0 v, terminated 1.0 v programmed swing, t rise 150 222 320 ps p 20% to 80%, vih = 1.0 v, vil = 0.0 v, terminated 1.0 v programmed swing, t fall 150 283 320 ps p 20% to 80%, vih = 1.0 v, vil = 0.0 v, terminated 2.0 v programmed swing, t rise 297 ps c b 20% to 80%, vih = 2.0 v, vil = 0.0 v, terminated 2.0 v programmed swing, t fall 322 ps c b 20% to 80%, vih = 2.0 v, vil = 0.0 v, terminated 3.0 v programmed swing, t rise 447 ps c b 20% to 80%, vih = 3.0 v, vil = 0.0 v, terminated 3.0 v programmed swing, t fall 397 ps c b 20% to 80%, vih = 3.0 v, vil = 0.0 v, terminated 5.0 v programmed swing, t rise 1117 ps c b 10% to 90%, vih = 5.0 v, vil = 0.0 v, unterminated 5.0 v programmed swing, t fall 798 ps c b 10% to 90%, vih = 5.0 v, vil = 0.0 v, unterminated rise to fall matching ?25 ps c b rise to fall within one channel, vih = 2.0 v, vil = 0.0 v, terminated ?61 ps c b rise to fall within one channel; vih = 1.0 v, vil = 0.0 v, terminated minimum pulse width toggle datx 0.5 v programmed swing 725 ps c b vih = 0.5 v, vil = 0.0 v, terminated, timing error less than +69/?33 ps 725 ps c b vih = 0.5 v, vil = 0.0 v, terminated, less than 10% amplitude loss maximum toggle rate 2040 mbps c b vih = 0.5 v, vil = 0.0 v, terminated, less than 10% loss at 50% duty 1.0 v programmed swing 725 ps c b vih = 1.0 v, vil = 0.0 v, terminated, timing error less than +58/?35 ps 725 ps c b vih = 1.0 v, vil = 0.0 v, terminated, less than 10% amplitude loss
adate318 rev. 0 | page 7 of 80 parameter min typ max unit test level conditions maximum toggle rate 2040 mbps c b vih = 1.0 v, vil = 0.0 v, terminated, less than 10% loss at 50% duty 2.0 v programmed swing 725 ps c b vih = 2.0 v, vil = 0.0 v, terminated, timing error less than +80/?48 ps 725 ps c b vih = 2.0 v, vil = 0.0 v, terminated, less than 10% amplitude loss maximum toggle rate 1400 mbps c b vih = 2.0 v, vil = 0.0 v, terminated, less than 10% loss at 50% duty 3.0 v programmed swing 900 ps c b vih = 3.0 v, vil = 0.0 v, terminated, timing error less than +50/?83 ps 900 ps c b vih = 3.0 v, vil = 0.0 v, terminated, less than 10% amplitude loss maximum toggle rate 1100 mbps c b vih = 3.0 v, vil = 0.0 v, terminated, less than 10% amplitude loss at 50% duty cycle dynamic performance, drive (vih to vil) toggle datx propagation delay time 1.26 ns c b vih = 2.0 v, vil = 0.0 v, terminated propagation delay tempco 1.4 ps/oc c b vih = 2.0 v, vil = 0.0 v, terminated delay matching, edge to edge 43 ps c b vih = 2.0 v, vil = 0.0 v, terminated, rising vs. falling delay matching, channel to channel 32 ps c b vih = 2.0 v, vil = 0.0 v, terminated, rising vs. rising, falling vs. falling delay change vs. duty cycle ?28 ps c b vih = 2.0 v, vil = 0.0 v, terminated, 5% to 95% duty cycle overshoot and undershoot ?116 mv c b vih = 2.0 v, vil = 0.0 v, terminated, driver clc set to 0 settling time (vih to vil) toggle datx to within 3% of final value 1.7 ns c b vih = 2.0 v, vil= 0.0 v, terminated to within 1% of final value 45 ns c b vih = 2.0 v, vil= 0.0 v, terminated dynamic performance, vterm (vih or vil to/from vit) toggle rcvx propagation delay time 1.39 ns c b vih = 2.0 v, vit = 1.0 v, vil = 0.0 v, terminated propagation delay tempco 2.3 ps/oc c b vih = 2.0 v, vit = 1.0 v, vil = 0.0 v, terminated transition time, active to vit 310 ps c b 20% to 80%, vih = 2.0 v, vit = 1.0 v, vil = 0.0 v, terminated transition time, vit to active 329 ps c b 20% to 80%, vih = 2.0 v, vit = 1.0 v, vil = 0.0 v, terminated dynamic performance, inhibit (vih or vil to/from inhibit) toggle rcvx transition time, inhibit to active 357 ps c b 20% to 80%, vih = +1.0 v, vil = ?1.0 v, terminated transition time, active to inhibit 1.34 ns c b 20% to 80%, vih = +1.0 v, vil = ?1.0 v, terminated prop delay, inhibit to vih 2.6 ns c b vih = +1.0 v, vil = ?1.0 v, terminated; measured from rcvx input crossing to dutx pin output 50% prop delay, inhibit to vil 2.8 ns c b vih = +1.0 v, vil = ?1.0 v, terminated prop delay matching, inhibit to vil vs. inhibit to vih 52 ps c b vih = +1.0 v, vil = ?1.0 v, terminated prop delay, vih to inhibit 2.29 ns c b vih = +1.0 v, vil = ?1.0 v, terminated, measured from rcvx input crossing to dutx pin output 50% prop delay, vil to inhibit 2.02 ns c b vih = +1.0 v, vil = ?1.0 v, terminated i/o spike 24 mv pk- pk c b vih = 0.0 v, vil = 0.0 v, terminated driver pre-emphasis (clc) pre-emphasis amplitude rising 35 % c b vih = 2.0 v, vil = 0.0 v, terminated, drv_clc_x[15:13] = 7 14 % c b vih = 2.0 v, vil = 0.0 v, terminated, drv_clc_x[15:13] = 0 pre-emphasis amplitude falling 24 % c b vih = 2.0 v, vil = 0.0 v, terminated, drv_clc_x[15:13] = 7 16 % c b vih = 2.0 v, vil = 0.0 v, terminated, drv_clc_x[15:13] = 0
adate318 rev. 0 | page 8 of 80 parameter min typ max unit test level conditions pre-emphasis resolution 2 % d pre-emphasis time constant 0.8 ns c b vih = 2.0 v, vil = 0.0 v, terminated table 3. reflection clamp (clamp accuracy specifications apply only when vch ? vcl > 0.8 v) parameter min typ max unit test level conditions vch/vcl programmable range ?2.5 +7.5 v d dc specif ications apply over full functional range unless noted. vch vch functional range ?1.2 +7.0 v d vch offset error ?300 +300 mv p driver high-z, sinking 1 ma, measured at dac code 0x4000, uncalibrated. vch offset tempco 0.5 mv/oc c t vch gain 1.0 1.1 v/v p driver high-z, sinking 1 ma, gain derived from measurements at dac code 0x 4000 (0 v) and dac code 0xc000 (5 v), based on ideal dac transfer function (see table 21 ). vch gain tempco 30 ppm/c c t vch resolution 153 v d vch dnl 1 mv c t driver high-z, sinking 1 ma, after two point gain/offset calibration; calibration points at dac code 0x4000 (0 v) and dac code 0xc000 (5 v), measured over functional clamp range. vch inl ?20 +20 mv p driver high-z, si nking 1 ma, after two point gain/offset calibration; calibration points at 0x4000 (0 v) and 0xc000 (5 v), measured over functional clamp range. vcl vcl functional range ?2 +6.2 v d vcl offset error ?300 +300 mv p driver hi gh-z, sourcing 1 ma, measured at dac code 0x4000, uncalibrated. vcl offset tempco 0.5 mv/c c t vcl gain 1.0 1.1 v/v p drive high-z, sourcing 1 ma, gain derived from measurements at dac code 0x 4000 (0 v) and dac code 0xc000 (5 v), based on ideal dac transfer function (see table 21 ). vcl gain tempco 30 ppm/c c t vcl resolution 153 v d vcl dnl 1 mv c t driver high-z, sourcing 1 ma, after two point gain/offset calibration; calibration points at 0x4000 (0 v) and 0xc000 (+5 v), measured over functional clamp range. vcl inl ?20 +20 mv p driver high-z, so urcing 1 ma, after two point gain/offset calibration; calibration points at 0x4000 (0 v) and 0xc000 (+5 v), measured over functional clamp range. dc clamp current limit, vch ?120 ?75 ma p driver high-z, vch = 0 v, vcl = ?2.0 v, vdutx = +5.0 v. dc clamp current limit, vcl +75 +120 ma p driver high-z, vch = +6.0 v, vcl = +5.0 v, vdutx = 0.0 v. dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range, measured at end points of vch and vcl functional range.
adate318 rev. 0 | page 9 of 80 table 4. normal window comparator (nwc) (unl ess otherwise specified: voh tests at vol = ? 1.5 v, vol tests at voh = + 6.5 v, specifications apply to both comparators) parameter min typ max unit test level conditions dc specifications input voltage range ?1.5 + 6.5 v d differential voltage range 0.1 8.0 v d comparator input offset voltage ?250 +250 mv p measured at dac code 0x4000 (0v), uncalibrated input offset voltage tempco 100 v/oc c t gain 1.0 1.1 v/v p gain derived from measurements at dac code 0x4000 (0 v) and dac code 0xc000 (5 v); based on ideal dac transfer function (see table 21 ) gain tempco 25 ppm/c c t threshold resolution 153 v d threshold dnl 1 mv c t measured over ? 1.5 v to + 6.5 v functional range after two point gain/offset calibration; calibration points at 0x4000 (0 v) and 0xc000 (5 v) threshold inl ?7 +7 mv p measured over ? 1.5 v to + 6.5 v functional range after two point gain/offset calibration; calibration points at 0x4000 (0 v) and 0xc000 (5 v) dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range; meas ured at end points of voh and vol functional range uncertainty band 5 mv c b vdutx = 0 v, sweep comparator threshold to determine the uncertainty band maximum programmable hysteresis 96 mv c b hysteresis resolution 5 mv d calculated over hystersis control code 10 to code 31 dc psrr 5 mv/v c t measured at calibration points digital output characteristics internal pull-up resistance to comparator, vttc 46 50 54 p pull 1 ma and 10 ma from logic 1 leg and measure ?v to calculate resistance; measured ?v/9 ma; done for both comparator logic states comparator termination voltage, vttc 0.5 1.2 3.3 v d common mode voltage vttc ? 0.3 v c t measured with 100 differential termination vttc ? 0.5 vttc v p measured with no external termination differential voltage 250 mv c t measured with 100 differential termination 450 500 550 mv p measured with no external termination rise/fall times, 20% to 80% 166 ps c b measured with 50 to external termination voltage (vttc) ac specifications all ac sp ecifications perfor med after dc level calibration, input transition time of ~200 ps, 20% to 80%, measured with 50 to external termination voltage (vttc); peaking set to clc = 2, unless otherwise specified propagation delay, input to output 0.93 ns c b vdutx: 0 v to 1.0 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.5 v propagation delay tempco 1.6 ps/oc c b vdutx: 0 v to 1.0 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.5 v propagation delay matching high transition to low transition 7 ps c b vdutx: 0 v to 1.0 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.5 v propagation delay matching high to low comparator 7 ps c b vdutx: 0 v to 1.0 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.5 v
adate318 rev. 0 | page 10 of 80 parameter min typ max unit test level conditions propagation delay dispersion slew rate 400 ps vs. 1 ns (20% to 80%) 19 ps c b vdutx: 0 v to 0.5 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.25 v overdrive 250 mv vs. 1.0 v 40 ps c b for 250 mv, vdutx: 0 v to 0.5 v swing; for 1.0 v, vdutx: 0 v to 1.25 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.25 v 1 v pulse width 0.7 ns, 1 ns, 5 ns, 10 ns +2/? 17 ps c b vdutx: 0 v to 1.0 v swing at~32.0 mhz; driver term mode, vit = 0.0 v, comparator threshold = 0.5 v 0.5 v pulse width 0.6 ns, 1 ns, 5 ns, 10 ns +3/? 24 ps c b vdutx: 0 v to 0.5 v swing at~32.0 mhz, driver term mode, vit = 0.0 v; compar ator threshold = 0.25 v duty cycle 5% to 95% 21 ps c b vdutx: 0 v to 1.0 v swing at~32.0 mhz; driver term mode, vit =0.0 v, comparator threshold = 0.5 v minimum detectable pulse width 0.5 ns c b vdutx: 0 v to 1.0 v swing at 32.0 mhz, driver term mode, vit = 0.0 v; greater than 50% output differential amplitude input equivalent bandwidth, terminated 1520 mhz c b vdutx: 0 v to 1.0 v swing; driver term mode, vit = 0.0 v, clc = 2; as measured by shmoo plot; f equiv = 0.22/ (t meas 2 ? t dut 2 ) ert high-z mode, 3 v, 20% to 80% 721 ps c b vdutx: 0 v to 3.0 v swing, driver high-z as measured by shmoo plot; f equiv = 0.22/ (t meas 2 C t dut 2 ) comparator pre-emphasis (clc) clc amplitude range 16 % c b vdutx: 0 v to 1.0 v swing, driver term mode, vit = 0.0 v, comparator pre-emphasis set to maximum clc resolution 2.3 % per bit c b 3-bit amplitude control pre-emphasis time constant 4.3 ns c b vdutx: 0 v to 1.0 v swing, driver term mode, vit = 0.0 v, comparator pre-emphasis set to maximum table 5. differential mode comparator (dmc) (u nless otherwise specified: voh tests at vol = ? 1.1 v, vol tests at voh = + 1.1 v) parameter min typ max unit test level conditions dc specifications input voltage range ?1.5 + 6.5 v d functional differential range 0.05 1.1 v d maximum differential input 8 v d input offset voltage ?250 +250 mv p offset extrapolated from measurements at dac code 0x2666 ( ? 1 v) and dac code 0x599a ( + 1 v), with v cm = 0 v offset voltage tempco 150 v/oc c t gain 1.0 1.1 v/v p gain derived from measurements at dac code 0x2666 (?1 v) and dac code 0x599a (+1 v), based on ideal dac transfer function (see table 21 ) gain tempco 25 ppm/c c t voh, vol resolution 153 v d voh, vol dnl 1 mv c t after two point gain/offset calibration, v cm = 0.0 v, calibration points at 0x2666 ( ? 1 v) and 0x599a ( +1 v) voh, vol inl ?7 +7 mv p after two point gain/offset calibration, measured over voh/vol range of ? 1.1 v to + 1.1 v, v cm = 0.0 v; calibration points at 0x2666 ( ? 1 v) and 0x599a ( +1 v) uncertainty band 7 mv c b vdutx = 0 v; sweep comparator threshold to determine the uncertainty band
adate318 rev. 0 | page 11 of 80 parameter min typ max unit test level conditions maximum programmable hysteresis 117 mv c b hysteresis resolution 5.6 mv d calculated over hystersis control code 10 to code 31 cmrr ?1 +1 mv/v p offset measured at v cm = ? 1.5 v and + 6.5 v with v dm = 0.0 v, offset error change dc psrr 5 mv/v c t measured at calibration points ac specifications all ac specificat ions performed after dc level calibration, unless noted; input transition time ~200 ps, 20% to 80%, measured with 50 to external termination voltage (vttc), peaking set to clc = 2, unless otherwise specified propagation delay, input to output 0.83 ns c b vdut0 = 0 v, vdut1: ? 0.5 v to + 0.5 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.0 v, repeat for other channel propagation delay tempco 2.6 ps/oc c b vdut0 = 0 v, vdut1: ? 0.5 v to + 0.5 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.0 v, repeat for other channel propagation delay matching, high transition to low transition 15 ps c b vdut0 = 0 v, vdut1: ? 0.5 v to + 0.5 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.0 v, repeat for other channel propagation delay matching, high to low comparator 17 ps c b vdut0 = 0 v, vdut1: ? 0.5 v to + 0.5 v swing, driver term mode, vit = 0.0 v, comparator threshold = 0.0 v, repeat for other channel propagation delay change (dispersion) with respect to slew rate: 400 ps and 1 ns (20% to 80%) 31 ps c b vdut0 = 0.0 v; vdut1: ? 0.5 v to + 0.5 v swing; driver term mode, vit = 0.0 v; comparator threshold = 0.0 v, repeat for other channel overdrive: 250 mv and 750 mv 32 ps c b vdut0 = 0.0 v; for 250 mv: vdut1: 0 v to 0.5 v swing; for 750 mv: vdut1: 0 v to 1.0 v swing; driver term mode, vit = 0.0 v; comparator threshold = ? 0.25 v; repeat for other channel with comparator threshold = +0.25 v 1 v pulse width: 0.7 ns, 1 ns, 5 ns, 10 ns +1/? 21 ps c b vdut0 = 0.0 v; vdut1: ? 0.5 v to + 0.5 v swing at 32 mhz; driver term mode, vit = 0.0 v; comparator threshold = 0.0 v; repeat for other channel 0.5 v pulse width: 0.6 ns, 1 ns, 5 ns, 10 ns +1/? 31 ps c b vdut0 = 0.0 v; vdut1: ? 0.25 v to + 0.25 v swing at 32 mhz; driver term mode, vit = 0.0 v; comparator threshold = 0.0 v; repeat for other channel duty cycle: 5% to 95% 18 ps c b vdut0 = 0.0 v; vdut1: ? 0.5 v to + 0.5 v swing at 32 mhz; driver term mode, vit = 0.0 v; comparator threshold = 0.0 v; repeat for other channel minimum detectable pulse width 0.5 ns c b vdut0 = 0.0 v; vdut1: ? 0.5 v to + 0.5 v swing at 32 mhz; driver term mode, vit = 0.0 v; comparator threshold = 0.0 v; greater than 50% output differential amplitude; repeat for other channel input equivalent bandwidth, terminated 1038 mhz c b vdut0 = 0.0 v; vdut1: ? 0.5 v to + 0.5 v swing; driver term mode, vit = 0.0 v; comparator threshold = 0.0 v, clc = 2 as measured by shmoo; repeat for other channel comparator pre-emphasis (clc) clc amplitude range 11 % c b vdut0 = 0.0 v; vdut1: ? 0.8 v to + 0.8 v swing, driver term mode, vit = 0.0 v; comparator threshold = 0.0 v; comparator clc set to maximum; repeat for other channel clc resolution 1.6 % per bit c b 3-bit amplitude control pre-emphasis time constant 4.8 ns c b vdut0 = 0.0 v; vdut1: ? 0.8 v to + 0.8 v swing, driver term mode, vit = 0.0 v; comparator threshold = 0.0 v; comparator clc set to maximum; repeat for other channel
adate318 rev. 0 | page 12 of 80 table 6. active load parameter min typ max unit test level conditions dc specifications load active on, rcvx active, unless otherwise noted input characteristics vcom voltage range ?1.5 + 6.5 v d | iol and ioh | 1 ma ?1.0 + 5.5 v d | iol and ioh | 25 ma vcom offset ?200 +200 mv p measured at dac code 0x4000, uncalibrated vcom offset tempco 25 v/c c t vcom gain 1.0 1.1 v/v p gain derived from measurements at dac code 0x4000 (0 v) and dac code 0xc000 ( + 5 v), based on ideal dac transfer function (see table 21 ) vcom gain tempco 25 ppm/c c t vcom resolution 153 v d vcom dnl 1 mv c t ioh = iol = 12.5 ma; after two point gain/offset calibration; measured over vcom range of ? 1.5 v to + 6.5 v; calibration points at 0x4000 (0 v) and 0xc000 ( + 5 v) vcom inl ?7 +7 mv p ioh = iol = 12.5 ma; after two point gain/offset calibration; measured at end points of vcom functional range dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range output characteristics maximum source current 25 ma d ? 1.5 v to + 5.5 v dut range iol offset ?600 +600 a p ioh = ?2.5 ma, vcom = 1.5 v, vdutx = 0.0 v; offset extrapolated from measurements at dac code 0x451f (1 ma) and dac code 0xa666 (20 ma) iol offset tempco 1 a/c c t iol gain error 0 25 % p ioh = ?2.5 ma, vcom = 1.5 v, vdutx = 0.0 v; gain derived from measurements at dac code 0x451f (1 ma) and dac code 0xa666 (20 ma); based on ideal dac transfer function (see table 21 and table 22 ) iol gain tempco 25 ppm/c c t iol resolution 763 na d iol dnl 4 a c t ioh = ?2.5 ma, vcom = 1.5 v, vdutx = 0.0 v; after two point gain/offset calibration; measured over iol range, 0 ma to 25 ma; calibrated at code 0x451f (1 ma) and code 0xa666 (20 ma) iol inl ?100 20 +100 a p ioh = ?2.5 ma, vcom = 1.5 v, vdutx = 0.0 v; after two point gain/offset calibration iol 90% commutation voltage 0.25 0.4 v p ioh = iol = 25 ma, vcom = 2.0 v; measure iol reference at vdutx = ?1.0 v; measure iol current at vdutx = 1.6 v; check >90% of reference current iol 90% commutation voltage 0.1 v c t ioh = iol = 1 ma, vcom = 2.0 v; measure iol reference at vdutx = ?1.0 v; measure iol current at vdutx = 1.9 v; check >90% of reference current maximum sink current 25 ma d ? 1.0 v to + 6.5 v output range ioh offset ?600 +600 a p iol = ?2.5 ma, vcom = 1.5 v, vdutx = 3.0 v; offset extrapolated from measurements at dac code 0x451f (1 ma) and dac code 0xa666 (20 ma) ioh offset tempco 1 a/c c t ioh gain error 0 25 % p iol = ?2.5 ma, vcom = 1.5 v, vdutx = 3.0 v; gain derived from measurements at dac code 0x451f (1 ma) and dac code 0xa666 (20 ma); based on ideal dac transfer function (see table 21 and table 22 )
adate318 rev. 0 | page 13 of 80 parameter min typ max unit test level conditions ioh gain tempco 25 ppm/c c t ioh resolution 763 na d ioh dnl 4 a c t iol = ?2.5 ma, vcom = 1.5 v, vdutx = 3.0 v; after two point gain/offset calibration; measured over ioh range, 0 ma to 25 ma; calibrated at code 0x451f (1 ma) and code 0xa666 (20 ma) ioh inl ?100 25 +100 a p iol = ?2.5 ma, vcom = 1.5 v, vdutx = 3.0 v; after two point gain/offset calibration ioh 90% commutation voltage 0.25 0.4 v p ioh = iol = 25 ma, vcom = 2.0 v; measure ioh reference at vdutx = 5.0 v; measure ioh current at vdutx = 2.4 v; ensure >90% of reference current 0.1 v c t ioh = iol = 1 ma, vcom = 2.0 v; measure ioh reference at vdutx = 5.0 v; measure ioh current at vdutx = 2.1 v; ensure >90% of reference current ac specifications all ac specificatio ns performed after dc level calibration unless noted; load active on dynamic performance propagation delay, load active on to load active off; 50%, 90% 3.1 ns c b toggle rcvx; dutx terminated 50 to gnd; iol = ioh = 20 ma, vih = vil = 0 v; vcom = + 1.5 v for iol and ? 1.5 v for ioh; measured from 50% point of rcvx ? rcvx to 90% point of final output; repeat for drive low and drive high propagation delay, load active off to load active on; 50%, 90% 4.1 ns c b toggle rcvx; dutx terminated 50 to gnd; iol = ioh = 20 ma, vih = vil = 0 v; vcom = + 1.5 v for iol and ? 1.5 v for ioh; measured from 50% point of rcvx ? rcvx to 90% point of final output; repeat for drive low and drive high propagation delay matching 1.0 ns c b toggle rcvx; dutx terminated 50 to gnd; iol = ioh = 20 ma, vih = vil = 0 v; vcom = + 1.5 v for iol and ? 1.5 v for ioh; active on vs. active off; repe at for drive low and drive high load spike 106 mv pk- pk c b toggle rcvx; dutx terminated 50 to gnd; iol = ioh = 0 ma, vih = vil = 0 v; vcom = + 1.5 v for iol and ? 1.5 v for ioh; repeat for drive low and drive high settling time to 90% 1.6 ns c b toggle rcvx; dutx terminated 50 to gnd; iol = ioh = 20 ma, vih = vil = 0 v; vcom = + 1.5 v for iol and ? 1.5 v for ioh; measured at 90% of final value table 7. ppmu (ppmu enabled in fv, dcl disabled) parameter min typ max unit test level conditions force voltage current range a ?40 +40 ma d current range b ?1 +1 ma d current range c ?100 +100 a d current range d ?10 +10 a d current range e ?2 +2 a d voltage range at output range a ?2.0 + 5.75 v d output range for full-scale source and sink. ?2.0 +6 v d output range for 25 ma. range b, range c, range d, and range e ?2.0 + 6.5 v d output range for full-scale source and sink. offset range c ?100 +100 mv p measured at dac code 0x4000 (0 v). all ranges 10 mv c t measured at dac code 0x4000 (0 v). offset tempco, all ranges 25 v/c c t
adate318 rev. 0 | page 14 of 80 parameter min typ max unit test level conditions gain range c 1.0 1.1 v/v p gain derived from measurements at dac code 0x4000 (0 v) and dac code 0xc000 (5 v); based on ideal dac transfer function (see table 21 and table 23). all ranges 1.05 v/v c t gain derived from measurements at dac code 0x4000 (0 v) and dac code 0xc000 (5 v); based on ideal dac transfer function (see table 21 and table 23). gain tempco, all ranges 25 ppm/c c t gain derived from measurements at dac code 0x4000 (0v) and dac code 0xc000 (5 v); calibration point 0x4000 (0 v) and 0xc000 (+5 v) output. inl range a 1 mv ct after two point gain/offset calibration, output range of ? 2.0 v to + 5.75 v, ppmu current range a only. range c ?1.7 + 1.7 mv p after two point gain/offset calibration; output range of ? 2.0 v to + 6.5 v. range b, range d, and range e 1 mv c t after two point gain/offset calibration, output range of ? 2.0 v to + 6.5 v. compliance vs. current load range a 40 mv c t force ? 2.0 v; measure voltage while sinking zero and full-scale current; measure v; force + 5.75 v; measure voltage while sourcing zero and full-scale current; measure v. 25 mv c t force ? 2.0 v; measure voltage while sinking zero and 25 ma current; measure v; force + 6 v; measure voltage while sourcing zero and 25 ma current; measure v. range b, range c, range d, and range e 1 mv c t force ? 2.0 v; measure voltage while sinking zero and full-scale current; measure v; force + 6.5 v; measure voltage while sourcing zero and full-scale current; measure v. current limit, source and sink all ranges 120 140 180 %fs p sink: force ? 2.0 v, short dutx to + 6.5 v; source: force + 6.5 v, short dutx to ? 2.0 v; repeat for each current range; example: range a fs = 40 ma, 120% fs = 48 ma 180% fs = 72 ma dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range; measured at endpoints of ppmu_vinfv functional range (see figure 136 ). measure current ppmu enabled in fimi, dcl disabled. dutx pin voltage range at full current range a ?2.0 +5.75 v d range b, range c, range d, and range e ?2.0 +6.5 v d zero-current offset, range b ?2 2 %fsr p interpolated from measurements sourcing and sinking 80% fsr current each range; fsr = 80 ma for range a, 2 ma for range b, 200 a for range c, 20 a for range d, 4 a for range e (see table 21 and table 23 ). all ranges 0.5 %fsr c t see table 21 and table 23 . zero-current offset tempco, range a 0.001 %fsr/c c t see table 21 and table 23 .
adate318 rev. 0 | page 15 of 80 parameter min typ max unit test level conditions range b, range c, and range d 0.001 %fsr/c c t range e 0.002 %fsr/c c t gain error range b ?30 +5 % p based on measurements sourcing and sinking, 80% fsr current. all ranges ?10 % c t based on measurements sourcing and sinking, 80% fsr current. gain tempco range a 50 ppm/c c t range b, range c, range d, and range e 25 ppm/c c t inl range a 0.0125 %fsr c t range a, after two point gain/offset calibration at 80% fsr current; measured over fsr output of ? 40 ma to +40 ma. range b ?0.03 +0.03 %fsr p after two point gain/offset calibration at 80% fsr current; measured over fsr output of ? 1 ma to +1 ma. range c, range d, and range e 0.01 %fsr c t after two point gain/offset calibration at 80% fsr current; measured over each fsr output for range c, range d, and range e. dutx pin voltage rejection ?1.2 + 1.2 a p range b, fvmi, force ?1 v and 5 v into load of 0.5 ma, measure i reported at ppmu_measx pin. dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range (see figure 136). force current ppmu enabled in fimi, dcl disabled. dutx pin voltage range in range a ?2.0 + 5.75 v d at full-scale source and sink current. ?2.0 +6 v d at 25 ma source and sink current. dutx pin voltage range at full current, range b, range c, range d, and range e ?2.0 + 6.5 v d zero-current offset, all ranges ?14.5 + 14.5 %fsr p extrapolated from measurements at code 0x4ccc and code 0xb333 for each range (see table 21 and table 23 ). zero-current offset tempco 0.002 %fsr/c c t gain error, all ranges ?5 +25 % p derived from measurements at code 0x4ccc and code 0xb333 for each range (see table 21 and table 23 ). gain tempco range a 50 ppm/c c t significant ppmu self-heating effects in range a can influence gain drift/tempco measurements. range b, range c, range d, and range e 25 ppm/c c t inl range a ?0.12 0.02 +0.12 %fsr p after two point gain/offset calibration; measured over fsr output of ? 40 ma to + 40 ma. range b, range c, and range d ?0.03 +0.03 %f sr p after two point gain/offset calibration; measured over fsr output; repeat for range b, range c, and range d.
adate318 rev. 0 | page 16 of 80 parameter min typ max unit test level conditions range e ?0.045 +0.045 %fsr p after two point gain/offset calibration; measured over fsr output. force current compliance vs. voltage load range a ?0.3 +0.3 %fsr p force po sitive full-scale current driving ?2.0 v and + 5.75 v; measure i at dutx pin; force negative full-scale current driving ?2.0 v and + 5.75 v; measure i at dutx pin. ?0.3 +0.3 %fsr p force +25 ma driving ?2.0 v and + 6.0 v; measure i at dutx pin; force ?25 ma driving ?2.0 v and + 6.0 v; measure i at dutx pin. ?0.06 +0.06 %fsr p force positive full-scale current driving 0.0 v and +4.0 v; measure i at dutx pin; force negative full-scale current driving 0.0 v and +4.0 v; measure i at dutx pin. range b and range c ?0.3 +0.3 %fsr p fo rce positive full-scale current driving ?2.0 v and +6.5 v; measure i at dutx pin; force negative full-scale current driving ?2.0 v and +6.5 v; measure i at dutx pin. ?0.06 +0.06 %fsr p force positive full-scale current driving 0.0 v and +4.0 v; measure i at dutx pin; force negative full-scale current driving 0.0 v and +4.0 v; measure i at dutx pin. range d ?0.3 +0.3 %fsr p force po sitive full-scale current driving ? 2.0 v and +6.5 v; measure i at dutx pin; force negative full-scale current driving ? 2.0 v and +6.5 v; measure i at dutx pin; allows for 10 na of dutx pin leakage. range e ?0.85 +0.85 %fsr p force positive full-scale current driving ? 2.0 v and +6.5 v; measure i at dutx pin; force negative full-scale current driving ? 2.0 v and +6.5 v; measure i at dutx pin; allows for 10 na of dutx pin leakage. measure voltage ppmu enabled, fvmv, dcl disabled. voltage range ?2.0 +6.5 v d offset ?25 +25 mv p range b, vdutx = 0 v; offset = (ppmu_meas ? vdutx). offset tempco 10 v/c c t gain 0.98 1.02 v/v p range b, ga in derived from measurements at vdutx = 0.0 v and +5.0 v. gain tempco 1 ppm/c c t inl ?1.7 + 1.7 mv p range b, measured over ? 2.0 v to + 6.5 v. measure pin dc characteristics output range ?2.0 + 6.5 v d dc output current 4 ma d output impedance 200 p ppmu enabled in fvmv, dcl disabled; source resistance: ppmu force + 6.5 v with 0 ma, + 4 ma load sink resistance: ppmu force ? 2.0 v with 0 ma, ? 4 ma load resistance = v/ i at ppmu_meas pin. output leakage current when tristated ?1 +1 a p tested at ? 2.0 v and + 6.5 v.
adate318 rev. 0 | page 17 of 80 parameter min typ max unit test level conditions output short-circuit current ?25 +25 ma p ppmu enabled in fvmv, dcl disabled; source: ppmu force + 6.5 v, ppmu_meas to ? 2.0 v sink: ppmu force ? 2.0 v, ppmu_meas to + 6.5 v ppmu_measx pin, output capacitance 2 pf s ppmu_measx pin, load capacitance 100 pf s maximum load capacitance. voltage clamps ppmu enabled in fimi, dcl disabled, ppmu clamps enabled; clamp accuracy specifica- tions apply only when vch > vcl. low clamp range (vcl) ?2.0 + 4.0 v d high clamp range (vch) 0.0 + 6.5 v d positive clamp voltage droop ?300 1 +300 mv p v seen at dutx pin, range a, vch = + 5.0 v, vcl = ? 1 v; ppmu force 5 ma and 40 ma into open. negative clamp voltage droop ?300 1 +300 mv p v seen at dutx pin, range a, vch = + 5.0 v, vcl = ? 1 v, ppmu force ?5 ma and 40 ma into open. offset, ppmu clamp vch/vcl ?300 +300 mv p range b, ppmu force 0.5 ma into open; vch measured at dac code 0x4000 (0 v) with vcl at code 0x0000 ( ? 2.5 v); vcl measured at dac code 0x4000 (0 v) with vch at 0xffff (+7.5 v). offset tempco, ppmu clamp vch/vcl 0.5 mv/c c t gain, ppmu clamp vch/vcl 1.0 1.2 v/v p range b, ppmu force 0.5 ma into open; vch gain derived from measurements at dac code 0x4000 (0 v) and dac code 0xc000 ( + 5.0 v) with vcl at code 0x0000 ( ? 2.5 v); vcl gain derived from measurements at dac code 0x4000 (0 v) and dac code 0xa666 ( + 4.0 v) with vch at 0xffff ( + 7.5 v). gain tempco, ppmu clamp vch/vcl 25 ppm/c c t inl, ppmu clamp vch/vcl ?20 +20 mv p range b, ppmu force 0.5 ma into open, after two point gain/offset calibration; measured over ppmu clamp functional range. dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range; measured at end points of clamp functional range. settling/switching times force voltage settling time to 0.1% of final value range a, 200 pf and 2000 pf load 10 s s ppmu enabled in fv, range a, dcl disabled; program vin steps from 0 v to 0.5 v and 5.0 v. range b, 200 pf and 2000 pf load 12 s s ppmu enabled in fv, range b, dcl disabled; program vin steps from 0 v to 0.5 v and 5.0 v. range c, 200 pf and 2000 pf load 32 s s ppmu enabled in fv, range c, dcl disabled; program vin steps from 0 v to 0.5 v and 5.0 v. force voltage settling time to 1.0% of final value range a, 200 pf & 2000 pf load 8.1 s c b ppmu enabled in fv, range a, dcl disabled; program vin steps from 0 v to 5.0 v. range b, 200 pf and 2000 pf load 8.1 s c b ppmu enabled in fv, range b, dcl disabled; program vin steps from 0 v to 5.0 v. range c, 200 pf and 2000 pf load 8.1 s c b ppmu enabled in fv, range c, dcl disabled; program vin steps from 0 v to 5.0 v.
adate318 rev. 0 | page 18 of 80 parameter min typ max unit test level conditions range a, 200 pf and 2000 pf load 2.5 s c b ppmu enabled in fv, range a, dcl disabled; program vin steps from 0 v to 0.5 v. range b, 200 pf and 2000 pf load 6.3 s c b ppmu enabled in fv, range b, dcl disabled; program vin steps from 0 v to 0.5 v. range c, 200 pf and 2000 pf load 8.1 s c b ppmu enabled in fv, range c, dcl disabled; program vin steps from 0 v to 0.5 v. force current settling time to 0.1% of final value range a, 200 pf in parallel with 120 16 s s ppmu enabled in fi, range a, dcl disabled; program vin step of 0 ma to 40 ma. range b, 200 pf in parallel with 1.5 k 10 s s ppmu enabled in fi, range b, dcl disabled; program vin step of 0 ma to 1 ma. range c, 200 pf in parallel with 15.0 k 40 s s ppmu enabled in fi, range c, dcl disabled; program vin step of 0 ma to 100 a. force current settling time to 1.0% of final value range a, 200 pf in parallel with 120 8.1 s c b ppmu enabled in fi, range a, dcl disabled; program vin step of 0 ma to 40 ma. range b, 200 pf in parallel with 1.5 k 7.5 s c b ppmu enabled in fi, range b, dcl disabled; program vin step of 0 ma to 1 ma. range c, 200 pf in parallel with 15.0 k 8.1 s c b ppmu enabled in fi, range c, dcl disabled; program vin step of 0 ma to 100 a. interaction and crosstalk measure voltage channel-to-channel crosstalk 0.01 %fsr c t 0.01% 8.5 v = 0.85 mv, ppmu enabled in fimv, dcl disabled; chx under test: range b, forcing 0 ma into 0 v load; other channel: range a, sweep 0 ma to 40 ma into 0 v load; report v of ppmu_measx pin under test. measure current channel-to-channel crosstalk 0.01 %fsr c t 0.01% 5.0 v = 0.5 mv, ppmu enabled in fvmi, dcl disabled; chx under test: range e, forcing 0 v into 0 ma current load; other channel: range e, sweep ? 2.0 v to +6.5 v into 0 ma current load; report v of ppmu_measx pin under test. table 8. ppmu_go/no-go comparators parameter min typ max unit test level conditions compare voltage range ?2.0 + 6.5 v d input offset voltage ?250 +250 mv p measured at dac code 0x4000 (0 v) input offset voltage tempco 50 v/oc c t gain 1.0 1.1 v/v p gain deri ved from measurements at dac code 0x4000 (0 v) and dac code 0xc000 (+5.0 v) gain tempco 25 ppm/oc c t applies at m = 1.0 and c = 0.0 comparator threshold resolution 153 v d comparator threshold dnl 1 mv c t after two point gain/offset calibration; measured over voh/vol range ? 2.0 v to + 6.5 v; calibration points at 0x4000 (0 v) and 0xc000 ( + 5 v) comparator threshold inl ?7 +7 mv p after two point gain/offset calibration; measured at end points of voh and vol functional range dutgnd voltage accuracy ?7 2 +7 mv p over 0.1 v range
adate318 rev. 0 | page 19 of 80 parameter min typ max unit test level conditions comparator uncertainty band 1.6 mv c b sweep comparator threshold to determine uncertainty (oscillation) band dc hysteresis <1 mv c b sweep comparator threshold comparator outputs ppmu_cmph x , ppmu_cmplx output logic high vdd/4 ? 0.5 vdd/4 + 0.5 v p f sourcing 100 a output logic low 0 0.5 v p f sinking 100 a table 9. ppmu_sense pin parameter min typ max unit test level condition pmu_sx (system pmu) sense pin characteristics voltage range ?2.0 +7.0 v d dcl high -z compliance range is ?2.0 v to +7.0 v ext sense switch r on 2.5 k p push 0.5 ma into pmu_sx with switch closed and dutx pin at 0 v; calculate r = v/0.0005 leakage ?2 +2 na p tested at ?2.0 v and +7.0 v, switch open pin capacitance (pmu_sx) 0.5 pf s switch open ppmu_sx (internal ppmu) sense pin characteristics voltage range ?2.0 + 6.5 v d ppmu input select in all states leakage ?2 +2 na p tested at ?2.0 v and + 6.5 v max load capacitance 2 nf s table 10. serial programma ble interface (spi) (sdi, rst , cs , sclk, sdo, busy ) parameter min typ max unit test level condition input logic high 1.8 vcc v p f sdi, rst , cs , sclk. input logic low 0 0.7 v p f input bias current ?10 1 +10 a p tested at 0.0 v and vcc volts. sclk clock rate 0.5 50 mhz d sclk pulse width, minimum 9 ns c t sclk crosstalk on dutx pin 30 mv c b dcl disabled; ppmu fv enabled and forcing 0.0 v. serial output logic high vcc ? 0.5 vcc v p f sdo; sourcing 2 ma. serial output logic low 0 0.5 v p f sinking 2 ma. busy pull-up voltage 2.3 2.5 3.5 v d busy is an open drain output that pulls low when the spi requires additional sclk cycles. busy active voltage 0.2 0.8 v p f busy active, sinking 2 ma.
adate318 rev. 0 | page 20 of 80 table 11. vhh driver (vhh mode enabled, rcv active) parameter min typ max unit test level conditions vhh buffer vhh mode enabled, rcvx active voltage range 0.0 13.5 v d output high 13.5 v p vhh level = full scale, sourcing 15 ma output low 5.9 v p vhh level = zero-scale, sinking 15 ma extrapolated offset ?500 +500 mv p extrapolated from measurements at dac code 0x8000 ( + 7 v) and dac code 0xc000 ( + 12 v) extrapolated offset tempco 0.5 mv/oc c t gain 2 2.2 v/v p gain derive d from measurements at dac code 0x8000 (+7 v) and dac code 0xc000 (+12 v); based on ideal dac transfer function (see table 21 ) gain tempco 25 ppm/oc c t resolution 305 v d inl ?25 +25 mv p vhh mode enabled, rcvx active; after two point gain/offset calibration; measured over +5.9 v to +13.5 v; calibrate at code 0x8000 (+7 v) and code 0xc000 (+12 v) dutgnd voltage accuracy 4 mv c t over 0.1 v range; measured at end points of vhh functional range output resistance 10 p v/ i; vhh mode enabled, rcvx active; source: vhh = +10.0 v, i = 0 ma, +15 ma sink: vhh = +6.5 v, i = 0 ma, ?15 ma dc output current limit source +60 +100 ma p vhh mode enabled, rcvx active; vhh = +13.5 v, short hvout pin to +5.9 v, measure current dc output current limit sink ?100 ?60 ma p vhh mode enabled, rcvx active, vhh = 5.9 v, short hvout pin to 13.5 v, measure current vhh rise time (from vil or vih to vhh) 163 ns c b 20% to 80%, vhh mode enabled, toggle rcvx: vhh = 13.5 v, vil = 0.0 v, vih = 3.0 v, datx = high; vhh = 13.5 v, vil = 3.0 v, vih = 4.0 v, datx = low vhh fall time (from vhh to vil or vih) 30 ns c b 20% to 80%, vhh mode enabled, toggle rcvx; vhh = 13.5 v, vil = 0.0 v, vih = 3.0 v, datx = high; vhh = 13.5 v, vil = 3.0 v, vih = 4.0 v, datx = low preshoot, overshoot, and undershoot 40.0 mv c b vhh mode enabled, toggle rcvx; vhh = 13.5 v, vil = 0.0 v, vih = 3.0 v, datx = high; vhh = 13.5 v, vil = 3.0 v, vih = 4.0 v, datx = low vil/vih drive function v hh mode enabled, rcvx inactive voltage range ?0.1 + 6.5 v d offset voltage ?500 +500 mv p measured at dac code 0x4000 (0 v), for datx = high and datx = low offset voltage tempco 1 mv/oc c t gain 1.0 1.1 v/v p gain deri ved from measurements at dac code 0x4000 (0 v) and dac code 0xc000 (5 v); based on ideal dac transfer function (see table 21 ) gain tempco 75 ppm/oc c t resolution 153 v d inl ?20 +20 mv p vhh mode enabled, rcvx inactive; after two point gain/offset calibration; measured over ?0.1 v to + 6.0 v; calibrate at code 0x4000 (0 v) and code 0xc000 (+5.0 v)
adate318 rev. 0 | page 21 of 80 parameter min typ max unit test level conditions dutgnd voltage accuracy 2 mv c t over 0.1 v range; measured at end points of vih and vil functional range output resistance 46 48 50 p v/ i; vhh mode enabled, rcvx inactive; source: vih = +3.0 v, i = + 1 ma, + 50 ma; sink: vil = +2.0 v; i = ?1 ma, ?50 ma dc output current limit source 60 100 ma p vhh mode enabled, rcvx inactive, vih = + 6.0 v, short hvout pin to ? 0.1 v, datx high, measure current dc output current limit sink ?100 ?60 ma p vhh mode enabled, rcvx inactive, vil = ?0.1 v, short hvout pin to + 6.0 v, datx low, measure current rise time, vil to vih 6.4 ns c b 20% to 80%, vhh mode enabled, rcvx inactive, vil = 0.0 v, vih = 3.0 v, r load > 500 , toggle datx fall time, vih to vil 7.3 ns c b 20% to 80%, vhh mode enabled, rcvx inactive, vil = 0.0 v, vih = 3.0 v, r load > 500 , toggle datx preshoot, overshoot, and undershoot 30 mv c b vhh mode enabled, rcvx inactive, vil = 0.0 v, vih = 3.0 v, r load > 500 , toggle datx table 12. alarm functions parameter min typ max unit test level condition dc characteristics overvoltage detect (ovd) see figure 137 programmable voltage range ? 2.5 + 7.5 v d uncalibrated error at ? 2.0 v ?200 +200 mv p measured at dac code 0x0ccc ( ? 2.0 v); ovd comparators not guaranteed to function as specified if vdutx is outside absolute maximum voltage range uncalibrated error at + 7.0 v ?450 +450 mv p measured at dac code 0xf333 ( + 7.0 v) offset voltage tempco 0.5 mv/c c t gain derived from measuremen ts at dac code 0x4000 and dac code 0xc000 gain 1.045 v/v c t hysteresis 125 mv c t thermal alarm see figure 137 setpoint error 10 c c t relative to default value, 100c thermal hysteresis ?15 c c t ppmu clamp alarm see figure 137 and table 29 for electrical characteristics alarm output characteristics off state leakage 10 500 na p disable alarm, apply 2.5 v to alarm pin, measure leakage current max on voltage at100 a 0.1 0.7 v p activate alarm, force 100 a into alarm pin, measure active alarm voltage propagation delay 1.5 s c b for ovd_hi: vdutx: 0 v to 6 v swing, ovdh = + 3.0 v, ovdl = ? 1.0 v for ovd_lo: vdutx: 0 v to 6 v swing, ovdh = + 7.0 v, ovdl= + 3.0 v
adate318 rev. 0 | page 22 of 80 spi timing details 09530-004 scl k cs sdi a0 d15 d14 01234567891011 2425 01234567 d1 c1 c0 a6 a5 a4 a3 a2 a1 c1 c0 a6 a5 a4 a3 a2 a1 a0 c1 c0 a6 a5 a4 a3 a2 a1 c1 c0 a6 a4 a3 a2 a1 a0 d15 d14 d1 d0 d0 sdo busy t ch t cl t csas t csah t cso t ds t dh t do t csam t csrs t csrh t csz t busa t busr t busw see table 18 note 1 note 1 notes 1. if the spi_sdo_hiz control bit (addr 0x12 [1]) is high, the sdo pin becomes active following the assertion of cs. it becomes high-z following release of cs. if the spi_sdo_hiz control bit is low, the sdo pin remains active independent of cs. r/w r/w figure 2. spi detailed read/write timing diagram 09530-005 scl k cs sdi sdo busy from previous spi instructions (see table 18) see table 18 ch[1:0] w addr[6:0] data[15:0] note 1 note 1 active ? output is the previous spi word shifted into sdi notes 1. if the spi_sdo_hiz control bit (addr 0x12 [1]) is high, the sdo pin becomes active following the assertion of cs. it becomes high-z following release of cs. if the spi_sdo_hiz control bit is low, the sdo pin remains active independent of cs. figure 3. spi write instruction
adate318 rev. 0 | page 23 of 80 09530-006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sclk rst busy dac 0 previous code default dac 0 code v dutgnd previous code default dac 1 code v dutgnd previous code default dac 23 code initialized condition reset condition v dutgnd dac 1 dac 23 t ch asynchronous assert t cl t rs t rmin t busa t busr t busw see table 18 3s (dac deglitch) figure 4. spi detailed hardware reset timing diagram
adate318 rev. 0 | page 24 of 80 0 9530-007 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sclk cs sdi spi reset busy dac 0 dac 1 dac 23 previous code default dac 0 code v dutgnd previous code default dac 1 code v dutgnd previous code default dac 23 code initialized condition reset condition v dutgnd t ch t cl t busa t busr t busw see table 18 3s (dac deglitch) figure 5. spi detailed soft ware reset timing diagram 09530-008 sclk cs sdi sdo busy from previous spi instructions (see table 18) ch[1:0] r addr[6:0] data[15:0] = don?t care note 1 note 1 active ? output is the previous spi word shifted into sdi notes 1. if the spi_sdo_hiz control bit (addr 0x12 [1]) is high, the sdo pin becomes active following the assertion of cs. it becomes high-z following release of cs. if the spi_sdo_hiz contro l bit is low, the sdo pin always remains active independent of cs. figure 6. spi read request instruction (prior to readout)
adate318 rev. 0 | page 25 of 80 09530-009 sclk cs sdi sdo busy see table 18 ch[1:0] r/w addr[6:0] (could be nop) ch[1:0] addr[6:0] 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data[15:0] = (if nop, then don?t care) note 1 note 2 note 1 read out data[15:0] notes 1. if the spi_sdo_hiz control bit (addr 0x12 [1]) is high, the sdo pin becomes active following the assertion of cs. it becomes high-z following release of cs. if the spi_sdo_hiz control bit is low, the sdo pin remains active independent of cs. 2. the first 10 bits of sdo following a read request echo address and channel bits of the preceding request. the r/w bit position is set low. the following 16 bits contain data from the requested address and channel. figure 7. spi readout instruction (subsequent to read request)
adate318 rev. 0 | page 26 of 80 table 13. spi detailed timing requirements parameter min max unit test level description f clk 0.5 50 mhz c t sclk operating frequency. t ch 9 ns c t sclk high time. t cl 9 ns c t sclk low time. t csas 3 ns c t setup of cs to rising sclk at assert. t csah 3 ns c t hold of cs to rising sclk at assert. t csrs 3 ns c t setup of cs to rising sclk at release. t csrh 3 ns c t hold of cs to rising sclk at release. 4 ns c t hold of cs release prior to rising sclk. this parameter is critical only if the number of sclk cycles from the previous release of cs is the minimum specified by the t csam parameter. t cso 6 ns c t delay from cs assert to sdo active. t csz 10 ns c t delay from cs release to sdo high-z, depends greatly on external pin loading. t csam 3 cycles c t width of cs release between consecutive assertions of cs . this parameter is specified in units of sclk cycles, more specifically in terms of rising edges of the sclk input. t ds 3 ns c t setup of sdi data prior to rising sclk. t dh 4 ns c t hold of sdi data following rising sclk. t do 12 ns c t delay of sdo data from rising sclk. t busa 12 ns c t delay of busy assert from first rising sclk following a valid cs release or an asynchronous rstb release. t busw 3 26 cycles c t width of busy assert. to ensure proper spi opera tion, the sclk must be provided for as long as busy remains asserted. note that the number of sclk cycles within any busy period is variable but deterministic and is based on the previous spi write instruction type. see the section and , use of the spi busy pin figure 3 figure 6 , , and for more information. figure 8 table 18 t busr 12 ns c t delay of busy release from first rising sclk, satisfying the requirements detailed in the section. use of the spi busy pin t rmin 10 ns c t width of asynchronous rst assert. t rs 3 ns c t setup of rst to rising sclk at release. t spi 29 cycles c t number of sclk rising edge cycles pe r spi word write plus the additional t csam requirement. t dac 5 10 s s settling time of analog dac levels to 0.5 lsb relative to the beginning of the dac deglitch period, which begins x sclk cycles following the release of cs and four sclk cycles prior to the release of the busy pin. the number of sclk cycles, x, is defined by . also see for more information. table 18 figure 124
adate318 rev. 0 | page 27 of 80 absolute maximum ratings table 14. absolute maximum ratings parameter rating supply voltages positive supply voltage (vdd to pgnd) ?0.5 v to +11.0 v positive vcc supply voltage (vcc to dgnd) ?0.5 v to +4.0 v negative supply voltage (vss to pgnd) ?6.5 v to +0.5 v supply voltage difference (vdd to vss) ?1.0 v to +17.0 v reference ground (dutgnd to agnd) ?0.5 v to +0.5 v vplus supply voltage (vplus to pgnd) ?0.5 v to +19.0 v supply sequence or dropout condition 1 input/output voltages analog input common-mode voltage vss to vdd dutx output short circuit voltage 2 ? 3.0 v to +8.0 v high speed input voltage absolute range 3 ?0.5 v to vttc + 0.5 v high speed differential input voltage 3 ?1.0 v to +1.0 v dutx i/o pin current dcl maximum short-circuit current 4 140 ma temperature operating temperature, junction 125c storage temperature range ?65c to +150c 1 no supply should exceed the given ratings. 2 r load = 0 , vdutx continuous short-circu it condition (vih, vil, vit), high-z, vcom, and clamp modes). 3 dat, dat , rcv, rcv , r source = 0 . 4 r load = 0 , vdutx = ?3 v to +8 v; dcl current limit. continuous short-circuit condition. adate318 current limits and survives a continuous short-circuit fault. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 15. thermal resistance package type ja jc unit airflow 0 1 2 m/s lfcsp 45 40 37 1 c/w table 16. explanation of test levels test level description d definition s design verification simulation p 100% production tested p f functionally checked during production test c t characterized on tester c b characterized on bench esd caution
adate318 rev. 0 | page 28 of 80 pin configuration and fu nction descriptions notes 1. exposed paddle is internally connected via high impedance to vss (substrate). 2. nc = this pin is open. no internal connection. 09530-002 1 vdd_therm 2 ppmu_s1 3 therm 4 dat1 5 dat1 6 nc 7 rcv1 8 rcv1 9 scap1 10 ffcapb1 11 ffcapa1 12 cmpl1 13 cmpl1 14 vttc1 15 cmph1 16 cmph1 17 pgnd 18 vdd 19 vss 20 ppmu_cmph1 22 agnd 23 ppmu_cmpl1 24 ppmu_meas1 25 dgnd 26 dutgnd 27 alarm 28 vss 29 dgnd 30 cs 31 busy 32 sdo 33 sclk 34 sdi 35 vcc 36 vdd 37 rst 38 vref 39 vrefgnd 40 ppmu_meas0 55 scap0 56 rcv0 57 rcv0 58 nc 59 dat0 60 dat0 61 hvout 62 ppmu_s0 63 vplus 54 ffcapb0 53 ffcapa0 52 cmpl0 51 cmpl0 50 vttc0 49 cmph0 48 cmph0 47 pgnd 46 vdd 45 vss 44 ppmu_cmph0 43 agnd 75 vss 76 vdd 77 pgnd 78 vss 79 vsso1 80 dut1 81 vddo1 82 vdd 83 pmu_s1 84 vss 74 agnd 73 vss 72 vdd 71 pgnd 70 vss 69 vsso0 68 dut0 67 vddo0 66 vdd 65 pmu_s0 64 vss adate318 top view (not to scale) 84-lead 10mm 10mm lfcsp (heatsink face up, die face down) 21 agnd 41 ppmu_cmpl0 42 agnd pin 1 identifier figure 8. lfcsp pin configuration table 17. pin function descriptions pin mnemonic description ep exposed paddle exposed pa ddle is internally connected via hi gh impedance to vss (substrate). 1 vdd_therm temperature sensor vdd supply. 2 ppmu_s1 ppmu external sens e connect, channel 1. 3 therm temperature se nsor analog output. 4 dat1 high speed data input, channel 1. 5 dat1 high speed data input complement, channel 1. 6 nc this pin is open. no internal connection. 7 rcv1 high speed receive input, channel 1. 8 rcv high speed receive input complement, channel 1. 9 scap1 ppmu external compensa tion capacitor, channel 1. 10 ffcapb1 ppmu external feed forwar d capacitor pin b, channel 1. 11 ffcapa1 ppmu external feed forward capacitor pin a, channel 1. 12 cmpl1 high speed comparator low output, channel 1. 13 cmpl1 high speed comparator low output complement, channel 1. 14 vttc1 comparator supply termination, channel 1. 15 cmph1 high speed comparator high output complement, channel 1. 16 cmph1 high speed comparator high output, channel 1. 17 pgnd power ground. 18 vdd vdd supply. 19 vss vss supply. 20 ppmu_cmph1 ppmu go/no-go compar ator high output, channel 1. 21 agnd analog ground. 22 agnd analog ground. 23 ppmu_cmpl1 ppmu go/no-go compar ator low output, channel 1.
adate318 rev. 0 | page 29 of 80 pin mnemonic description 24 ppmu_meas1 ppmu analog measure output, channel 1. 25 dgnd digital logic ground. 26 dutgnd dut ground sense input. 27 alarm fault alarm open drain output. 28 vss vss supply. 29 dgnd digital logic ground. 30 cs serial programmable interface (spi ) chip select input (active low). 31 busy serial programmable interface (spi) busy output (active low). 32 sdo serial programmable interf ace (spi) serial data output. 33 sclk serial programmable interface (spi) clock input. 34 sdi serial programmable interf ace (spi) serial data input. 35 vcc vcc supply. 36 vdd vdd supply. 37 rst reset input (active low). 38 vref dac precision +5.0 v reference input. 39 vrefgnd dac precision +0.0 v reference input. 40 ppmu_meas0 ppmu analog measure output, channel 0. 41 ppmu_cmpl0 ppmu go/no-go compar ator low output, channel 0. 42 agnd analog ground. 43 agnd analog ground. 44 ppmu_cmph0 ppmu go/no-go compar ator high output, channel 0. 45 vss vss supply. 46 vdd vdd supply. 47 pgnd power ground. 48 cmph0 high speed comparator high output, channel 0. 49 cmph0 high speed comparator high output complement, channel 0. 50 vttc0 comparator supply termination, channel 0. 51 cmpl0 high speed comparator low output complement, channel 0. 52 cmpl0 high speed comparator low output, channel 0. 53 ffcapa0 ppmu external feed forward capacitor pin a, channel 0. 54 ffcapb0 ppmu external feed forwar d capacitor pin b, channel 0. 55 scap0 ppmu external compensa tion capacitor, channel 0. 56 rcv0 high speed receive input complement, channel 0. 57 rcv0 high speed receive input, channel 0. 58 nc this pin is open. no internal connection. 59 dat0 high speed data input complement, channel 0. 60 dat0 high speed data input, channel 0. 61 hvout vhh output pin. 62 ppmu_s0 ppmu external sens e connect, channel 0. 63 vplus vplus supply. 64 vss vss supply. 65 pmu_s0 system pmu sense input, channel 0. 66 vdd vdd supply. 67 vddo0 vdd supply, driver output stage, channel 0. 68 dut0 dut pin, channel 0. 69 vsso0 vss supply, driver output stage, channel 0. 70 vss vss supply. 71 pgnd power ground. 72 vdd vdd supply. 73 vss vss supply. 74 agnd analog ground.
adate318 rev. 0 | page 30 of 80 pin mnemonic description 75 vss vss supply. 76 vdd vdd supply. 77 pgnd power ground. 78 vss vss supply. 79 vsso1 vss supply, driver output stage, channel 1. 80 dut1 dut pin, channel 1. 81 vddo1 vdd supply, driver output stage, channel 1. 82 vdd vdd supply. 83 pmu_s1 system pmu sense input, channel 1. 84 vss vss supply.
adate318 rev. 0 | page 31 of 80 typical performance characteristics 09530-101 0.05 ?0.05 0 0.10 ?0.10 0.15 0.20 0.25 0.30 0.35 0246 time (ns) 8 101214161820 voltage (v) 500mv 200mv 09530-104 ?0.2 ?0.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.8 0 2 4 6 8 10 12 14 16 18 voltage (v) 20 time (ns) 1v 2v 3v figure 12. 100 mhz driver response, vih = 1. 0 v, 2.0 v, 3.0 v; vil = 0.0 v, 50 termination figure 9. driver small signal response, vih = 0.2 v, 0.5 v, vil = 0.0 v, 50 termination 09530-105 ?0.2 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.8 0246 voltage (v) 10 8 time (ns) 1v 2v 3v 09530-102 ?0.2 ?0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2 4 6 8 101214161820 voltage (v) time (ns) 2v 1v 3v figure 13. 300 mhz driver response, vih = 1.0 v, 2.0 v, 3.0 v; vil = 0.0 v, 50 termination figure 10. driver large signal response, vih = 1.0 v, 2.0 v, 3.0 v; vil = 0.0 v, 50 termination 09530-106 ?0.2 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.8 0246 voltage (v) 10 8 0.5v 1v 2v 3v time (ns) 1v 5v 3v 09530-103 ?1 0 1 2 3 4 5 6 0 2468101214161820 voltage (v) time (ns) figure 11. driver large signal response, vih = 1.0 v, 3.0 v, 5.0 v; vil = 0.0 v, 50 unterminated figure 14. 400 mhz driver response, vih = 0.5 v, 1.0 v, 2.0 v, 3.0 v; vil = 0.0 v, 50 termination
adate318 rev. 0 | page 32 of 80 09530-108 ?0.2 1.2 1.0 0.8 0.6 0.4 0.2 0 0123 voltage (v) 5 4 time (ns) 0.5v 1v 2v figure 15. 600 mhz driver response, vih = 0.5 v, 1.0 v, 2.0 v; vil = 0.0 v, 50 termination 09530-109 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 voltage (v) time (ns) vih to/from vit vil to/from vit figure 16. driver active (vih/vil) to/from vterm transition; vih = 1.0 v, vit = 0.5 v; vil = 0.0 v, 50 termination 09530-110 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 0 51 01 5 2 0 voltage (v) time (ns) vil to/from vit vih to/from vit figure 17. driver active (vih/vil) to/from vterm transition; vih = 2.0 v, vit = 1.0 v; vil = 0.0 v, 50 termination 09530-111 ?0.2 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 051 0 voltage (v) 20 15 time (ns) vih to/from vit vil to/from vit figure 18. driver active (vih/vil) to /from vterm transition; vih =3.0 v, vit = 1.5 v; vil = 0.0 v, 50 termination 09530-112 ?10 ?30 ?50 70 90 50 30 10 02 pulse width (ns) 46 trailing edge error (ps) 10 8 positive pulse negative pulse figure 19. driver trailing edge timing error pulse width, vih = 0.2 v; vil = 0.0 v, 50 termination 09530-113 ?10 ?30 ?50 70 90 50 30 10 02 pulse width (ns) 46 trailing edge error (ps) 10 8 positive pulse negative pulse figure 20. driver trailing edge timing error vs. pulse width, vih = 0.5 v; vil = 0.0 v, 50 termination
adate318 rev. 0 | page 33 of 80 09530-114 ?10 ?30 ?50 70 50 30 10 0 02 pulse width (ns) 46 trailing edge error (ps) 10 8 positive pulse negative pulse figure 21. driver trailing edge timing error vs. pulse width, vih = 1.0 v; vil = 0.0 v, 50 termination 09530-115 ?10 ?30 ?50 70 90 50 30 10 02 pulse width (ns) 46 trailing edge error (ps) 10 8 positive pulse negative pulse figure 22. driver trailing edge timing error vs. pulse width, vih = 2.0 v; vil = 0.0 v, 50 termination 09530-116 ?20 ?80 ?60 ?40 ?100 80 100 60 40 20 0 02 pulse width (ns) 46 trailing edge error (ps) 10 8 positive pulse negative pulse figure 23. driver trailing edge timing error vs. pulse width, vih = 3.0 v; vil = 0.0 v, 50 termination 09530-117 0 ?0.5 ?1.0 1.5 1.0 0.5 ?2 0 ?1 driver output voltage (v) 3 14 2 linearity error (mv) 7 56 figure 24. driver vih linearity error 09530-118 0 ?0.5 ?1.0 1.5 1.0 0.5 ?2 0 ?1 driver output voltage (v) 3 14 2 linearity error (mv) 7 56 figure 25. driver vil linearity error 09530-119 0 ?0.5 ?1.0 1.5 1.0 0.5 ?2 0 ?1 driver output voltage (v) 3 14 2 linearity error (mv) 7 56 figure 26. driver vit linearity error
adate318 rev. 0 | page 34 of 80 09530-120 0.10 0.20 0.15 ?0.05 0 0.05 ?0.10 0.25 0 ?1?2 2 1 vil programmed dac voltage (v) 4 35 interaction error (mv) 76 figure 27. driver interaction erro r vih vs. vil, vih = +6.5 v, vil swept from ?1.5 v to +6.5 v 09530-121 0.02 0.06 0.04 ?0.04 ?0.02 0 ?0.06 0.08 0 ?1?2 2 1 vih programmed dac voltage (v) 4 35 interaction error (mv) 76 figure 28. driver interaction error vil vs. vih; vil = ?1.5 v, vih swept from ?1.5 v to +6.5 v 09530-122 0.4 0.6 0.7 0.5 0.1 0 0.2 0.3 ?0.1 0.8 0 ?1?2 2 1 vih programmed dac voltage (v) 4 35 interaction error (mv) 76 figure 29. driver interaction error vi t vs. vih, vit = +1.0 v, vih swept from ?1.5 v to +6.5 v 09530-123 49.0 49.5 48.0 48.5 47.5 50.0 ?40 ?20 ?60 0 driver output current (ma) 20 driver output resistance ( ? ) 60 40 figure 30. driver output resistance vs. output current 09530-124 40 100 80 60 0 20 120 0 ?1 ?2 2 1 v dut (v) 4 35 driver output current (ma) 76 figure 31. driver output current limit; driver programmed to ?1.5 v, vdut swept ?1.5 v to +6.5 v 09530-125 ?80 ?20 ?40 ?60 ?120 ?100 0 0 ?1 ?2 2 1 v dut (v) 4 35 driver output current (ma) 76 figure 32. driver output current limit. driver programmed to 6.5 v, vdut swept ?1.5 v to +6.5 v
adate318 rev. 0 | page 35 of 80 09530-126 6 2 4 0 14 16 vhh output 12 10 8 00 . 5 time (s) 1.0 voltage (v) 2.0 1.5 figure 33. hvout transient response, vhh = 13.5 v 09530-127 ?2 ?4 ?5 ?6 ?3 ?7 2 3 1 0 ?1 ?1 1 hvout output voltage (v) 3 linearity error (mv) 7 5 0 246 figure 34. hvout vih linearity error 09530-128 ?2 ?4 ?5 ?6 ?3 ?7 2 3 1 0 ?1 ?1 1 hvout output voltage (v) 3 linearity error (mv) 7 5 0 246 figure 35. hvout vi l linearity error 09530-129 ?10 ?5 ?15 10 5 0 1 hvout output voltage (v) 3 linearity error (mv) 7 8 9 101112131415 5 0 246 figure 36. hvout vhh linearity error 09530-130 60 70 50 100 90 30 20 10 0 80 40 v hvout (v) hvout driver current (ma) 789101112131415 56 figure 37. hvout vhh output current limit; vhh = 5.9 v, hvout swept 5.9 v to 13.5 v 09530-131 ?20 ?10 ?30 20 10 ?50 ?60 ?70 ?80 ?90 0 ?40 v hvout (v) hvout driver current (ma) 789101112131415 56 figure 38. hvout vhh output current limit; vhh = 13.5 v, hvout swept 5.9 v to 13.5 v
adate318 rev. 0 | page 36 of 80 09530-132 ?10 70 80 60 50 40 30 20 10 0 ?1 1 v hvout (v) 3 hvout driver current (ma) 7 5 0246 figure 39. hvout vil output current limit; vil = ?0.1 v, hvout swept ?0.1 v to 6.0 v 09530-133 ?20 ?10 ?30 10 0 ?50 ?60 ?70 ?80 ?90 ?40 v hvout (v) hvout driver current (ma) 1234567 ?1 0 figure 40. hvout vih output current limit; vih = 6.0 v, hvout swept ?0.1 v to 6.0 v 09530-134 0.4 0 0.2 ?0.2 1.0 1.2 0.8 input edge 0.6 0 2 time (ns) 4 voltage (v) 81 6 0 shmoo figure 41. normal window comparator shmoo 1.0 v swing; 50 termination, 200 ps (20% to 80%) 09530-190 0.4 0 0.2 ?0.2 1.0 1.2 0.8 input edge 0.6 0 2 time (ns) 4 voltage (v) 81 6 0 shmoo figure 42. normal window comparator shmoo; 1.0 v swing, 50 termination, 200 ps (20% to 80%) 09530-191 ?15 ?25 ?20 ?30 0 5 ?5 ?10 0 2 pulse width (ns) 4 trailing edge (ps) 81 6 0 positive pulse negative pulse figure 43. normal window comparator trailing edge timing error vs. input pulse width; 50 termination, 1.0 v swing, 200 ps (20% to 80%) 09530-192 ?4 ?8 ?10 ?12 ?14 ?16 ?6 ?18 0 ?2 0.4 0.5 input transition time (20%/80%) (ns) 0.6 propagation delay variation (ps) 0.8 0.9 1.0 0.7 input voltage swing = 1v comparator threshold = 0.5v input rising edge input falling edge figure 44. normal window comparator input transition time (20%/80%), 50 termination
adate318 rev. 0 | page 37 of 80 09530-138 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5 10 15 20 voltage (v) time (ns) figure 45. comparator output waveform 09530-139 ?0.8 ?0.2 ?0.4 ?0.6 ?2.0 ?1.0 ?1.2 ?1.4 ?1.6 ?1.8 0 0 ?1?2 21 threshold voltage (v) 4 35 linearity error (mv) 76 figure 46. normal window comparator threshold linearity error 09530-140 0.5 0 1.0 1.5 ?1.0 ?1.5 ?0.5 ?2.0 2.0 ?1.0 ?0.5 ?1.5 0 threshold voltage (v) 0.5 linearity error (mv) 1.5 1.0 figure 47. differential comparator threshold linearity error 09530-141 0 0.05 ?0.05 0.20 0.15 ?0.15 ?0.20 ?0.25 0.10 ?0.10 ?2 threshold voltage (v) ?1 linearity error (mv) 234567 ?3 01 figure 48. ppmu go/no-go comparator linearity error 09530-142 1.5 2.0 0 1.0 0.5 2.5 0 ?1?2 21 input common-mode voltage (v) 4 35 differential comparator offset (mv) 76 figure 49. differential comparator cmr error 09530-143 ?5 0 5 10 15 20 25 30 0 51 01 51 5 load current (ma) time (ns) 2 0 current vil to load current load to vil figure 50. active load response to/from drive vil = 0 v, 50 termination, iol = 25 ma, vcom = 2 v
adate318 rev. 0 | page 38 of 80 09530-144 10 0 30 20 ?20 ?30 ?10 ?2 v dut (v) ?1 load current (ma) 234567 ?3 0 1 figure 51. active load commutation response, vcom = 2.0 v, ioh = iol = 25 ma 09530-145 5 15 10 ?10 ?5 0 ?15 20 5 01 0 active load current (ma) 15 20 linearity error (a) 25 figure 52. active load ioh linearity error 09530-146 ?0.8 ?0.2 ?0.4 ?0.6 ?1.0 ?1.2 0 0 ?1?2 2 1 vcom voltage (v) 4 35 linearity error (mv) 76 figure 53. active load vcom linearity error 09530-147 4 2 8 6 ?4 ?2 0 ?6 10 5 0 10 active load current (ma) 15 20 linearity error (a) 25 figure 54. active load iol linearity error 09530-148 ?2.0 ?1.5 ?2.5 0 ?0.5 ?3.5 ?4.0 ?4.5 ?1.0 ?3.0 ?2 v dut (v) ?1 leakage (na) 234567 ?3 0 1 figure 55. dutx pin leakage in low leakage mode 09530-149 150 100 250 200 0 ?50 50 ?2 v dut (v) ?1 leakage (na) 2345678 ?3 0 1 figure 56. dutx pin leakage in high-z mode
adate318 rev. 0 | page 39 of 80 09530-150 2.0 1.5 3.0 2.5 0.5 0 1.0 dutgnd voltage (v) ?0.10 error (mv) 0 0.05 0.10 0.15 ?0.15 ?0.05 figure 57. typical dutgnd transfer function voltage error, drive low vil = 0 v 09530-151 ?0.2 ?0.3 0.1 0 ?0.1 ?0.4 ?0.5 0.2 0 ?1?2 21 pmu output voltage (v) 4 35 linearity error (mv) 76 figure 58. ppmu force voltage linearity error, all ranges 09530-152 0 ?5 10 5 ?10 15 ?30 ?20 ?10 ?40 0 pmu output current (ma) 10 20 linearity error (a) 4030 figure 59. ppmu range a force current linearity error 09530-153 ?0.05 0.10 0.05 0 ?0.15 ?0.10 0.15 ?0.5 ?1.0 0 pmu output current (ma) 0.5 linearity error (a) 1.0 figure 60. ppmu range b force current linearity error 09530-154 0.016 0.012 0.010 0.004 0.002 0 0.006 0.014 0.008 0.018 ?0.05 ?0.10 0 pmu output current (ma) 0.05 linearity error (a) 0.10 figure 61. ppmu range c force current linearity error 09530-155 0.0005 ?0.0005 ?0.0010 0 0.0010 0.0015 ?0.005 ?0.010 0 pmu output current (ma) 0.005 linearity error (a) 0.010 figure 62. ppmu range d force current linearity error
adate318 rev. 0 | page 40 of 80 09530-156 ?0.0001 ?0.0003 ?0.0004 ?0.0005 ?0.0002 ?0.0006 0.0003 0.0004 0.0002 0.0001 0 ?0.0020 ?0.0010 pmu output current (ma) 0 linearity error (a) 0.0020 0.0010 ?0.0015 ?0.0005 0.0005 0.0015 figure 63. ppmu range e force current linearity error 09530-157 0 ?10 ?15 ?20 ?5 ?25 20 25 15 10 5 ?40 ?20 i dut (ma) 0 error (mv) 40 20 ?30 ?10 10 30 figure 64. ppmu force voltage range a compliance error at ?2.0 v vs. output current, internal sense 09530-158 0 ?10 ?15 ?20 ?5 ?25 20 25 15 10 5 ?40 ?20 i dut (ma) 0 error (mv) 40 20 ?30 ?10 10 30 figure 65. ppmu force voltage range a compliance error at +5.75 v vs. output current, internal sense 09530-159 ?0.1 0.4 0.3 0.1 0.2 0 ?0.5 ?0.2 ?0.3 ?0.4 0.5 ?0.5 ?1.0 0 i dut (ma) 0.5 error (mv) 1.0 figure 66. ppmu force voltage range b compliance error at ?2.0 v vs. output current, internal sense 09530-160 ?0.1 0.3 0.1 0.2 0 ?0.2 ?0.3 ?0.4 ?0.5 ?1.0 0 i dut (ma) 0.5 error (mv) 1.0 figure 67. ppmu force voltage range b compliance error at +6.5 v vs. output current, internal sense 09530-161 0 ?5 10 5 20 15 ?1 0 1 ?2 2 v dut (v) 34 error (a) 65 figure 68. ppmu force current range a compliance error at ?40 ma vs. output voltage
adate318 rev. 0 | page 41 of 80 09530-162 0 ?5 10 5 20 25 30 35 15 ?1 0 1 ?2 2 v dut (v) 34 error (a) 65 figure 69. ppmu force current range a compliance error at +40 ma vs. output voltage 09530-163 0 ?0.05 0.10 0.05 0.20 0.25 0.30 0.15 ?1 0 1 ?2 2 v dut (v) 34 error (a) 67 5 figure 70. ppmu force current range b compliance error at ?1 ma vs. output voltage 09530-164 0 ?0.1 0.2 0.1 0.3 0.4 0.5 ?1 0 1 ?2 2 v dut (v) 34 error (a) 67 5 figure 71. ppmu force current range b compliance error at +1 ma vs. output voltage 09530-165 ?0.0005 ?0.0010 0.0005 0 0.0010 0.0015 0.0020 ?1 0 1 ?2 2 v dut (v) 34 error (a) 67 5 figure 72. ppmu force current range e compliance error at ?2 a vs. output voltage 09530-166 ?0.0005 0.0005 0 0.0010 0.0015 0.0020 ?1 0 1 ?2 2 v dut (v) 34 error (a) 67 5 figure 73. ppmu force current range e compliance error at +2 a vs. output voltage 09530-167 20 10 30 0 40 50 60 ?1 0 1 ?2?3 2 v dut (v) 34 ppmu output current (ma) 67 5 figure 74. ppmu force voltage output current limit range a, fv = ?2.0 v, vdut swept ?2.0 v to +6.5 v
adate318 rev. 0 | page 42 of 80 09530-168 ?50 ?60 ?30 ?40 ?20 ?10 0 10 ?1 0 1 ?2?3 2 v dut (v) 34 ppmu output current (ma) 67 5 figure 75. ppmu force voltage output current limit range a, fv = +6.5 v, vdut swept ?2.0 v to +6.5 v 09530-169 2.65 2.60 2.75 2.70 2.80 2.85 2.90 ?1 0 1 ?2?3 2 v dut (v) 34 ppmu output current (a) 67 5 figure 76. ppmu force voltage output current limit range e, fv = ?2.0 v, vdut swept ?2.0 v to +6.5 v 09530-170 ?3 ?4 ?1 ?2 0 1 2 3 ?1 0 1 ?2?3 2 v dut (v) 34 ppmu output current (a) 67 5 figure 77. ppmu force voltage output current limit range e, fv = 6.5 v, vdut swept ?2.0 v to +6.5 v 09530-171 0 0.02 ?0.02 0.03 ?0.03 0.04 ?0.04 ?0.05 ?0.06 0.01 ?0.01 ?1 0 1 ?2 2 v dut (v) 34 linearity error (mv) 67 5 figure 78. ppmu range b measure voltage linearity error 09530-172 0.10 0.06 0.04 ?0.02 ?0.04 ?0.06 0 0.08 0.02 0.12 ?0.5 ?1.0 0 i dut (ma) 0.5 linearity error (a) 1.0 figure 79. ppmu range b measure current linearity error 09530-173 0.10 ?0.10 ?0.15 ?0.20 ?0.25 ?0.30 ?0.35 ?0.40 ?0.45 0.05 ?0.05 0 ?1 0 1 ?2 2 v dut (v) 34 ppmu_meas0 pin error (mv) 1mv = ~400na 65 figure 80. ppmu measure current cmr error, (fvmi), sourcing 0.5 ma
adate318 rev. 0 | page 43 of 80 09530-174 0.4 0.6 0.2 1.2 1.0 ?0.2 ?0.4 ?0.6 0.8 0 ?2 output voltage (v) ?1 linearity error (mv) 234567 ?3 01 figure 81. reflection cl amp vcl linearity error 09530-175 0.1 0.2 0.5 0.4 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0.3 0 ?2 output voltage (v) ?1 linearity error (mv) 234 5678 01 figure 82. reflection clamp vch linearity error 09530-176 1 2 ?2 ?1 ?3 ?4 ?5 0 ?2 ?3 output voltage (v) ?1 linearity error (mv) 2345 01 figure 83. ppmu voltage clamp vcl linearity error 09530-177 1.5 1.0 0.5 2.0 ?0.5 ?1.0 ?1.5 ?2.0 0 output voltage (v) linearity error (mv) 234567 01 figure 84. ppmu voltage clamp vch linearity error 09530-178 0 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 ?90 ?100 ?2?3 v dut (v) ?1 output current (ma) 23456 01 figure 85. vcl reflection clamp current limit; vch = 6 v, vcl = 5 v, vdut swept ?2.0 v to +5.0 v 09530-179 90 30 40 50 60 70 80 20 10 0 10 v dut (v) 2 output current (ma) 45678 3 figure 86. vch reflection clamp curren t limit; vch = 0 v, vcl = ?2 v, vdut swept ?2.0 v to +5.0 v
adate318 rev. 0 | page 44 of 80 09530-180 0 ?120 ?100 ?80 ?60 ?40 ?20 ?140 ?160 ?180 10 driver clc setting 3-bit value 2 offset (mv) 4567 3 figure 87. driver offset error vs. driver clc setting 09530-181 20 ?5 0 5 10 15 ?10 ?15 ?20 10 comparator clc setting 3-bit value 2 offset (mv) 4567 3 figure 88. normal window comparator offset error vs. clc setting 09530-182 20 ?5 0 5 10 15 ?10 ?15 ?20 10 differential comparator clc setting 3-bit value 2 offset (mv) 4567 3 figure 89. differential comparator offset error vs. clc setting 09530-208 60 40 0 50 30 20 10 90 100 80 70 05 hysteresis code measured hysteresis (mv) 25 30 35 10 15 20 resolution (0 to 31) = ~ 3.0mv/bit resolution (10 to 31) = ~ 4.6mv/bit vol_hysteresis voh_hysteresis figure 90. normal window comparator hysteresis transfer function 09530-209 80 60 0 40 20 140 120 100 05 hysteresis code measured hysteresis (mv) 25 30 35 10 15 20 resolution (0 to 31) = ~ 3.6mv/bit resolution (10 to 31) = ~ 5.6mv/bit vol_hysteresis voh_hysteresis figure 91. differential comparator hysteresis transfer function 09530-183 1ns/div c1 100mv/di v figure 92. driver eye diagram, 400 mbps, prbs31; vih = 1 v, vil = 0 v
adate318 rev. 0 | page 45 of 80 09530-184 500ps/div c1 100mv/di v figure 93. driver eye diagram, 800 mbps, prbs31; vih = 1 v, vil = 0 v 09530-185 500ps/div 200mv/di v c1 figure 94. driver eye diagram, 800 mbps, prbs31; vih = 2 v, vil = 0 v 09530-186 200ps/div c1 100mv/di v figure 95. driver eye diagram, 1600 mbps, prbs31; vih = 1 v, vil = 0 v 09530-187 200ps/div c1 200mv/di v figure 96. driver eye diagram, 1600 mbps, prbs31; vih = 2 v, vil = 0 v 09530-188 200ps/div c1 100mv/di v figure 97. driver eye diagram, 2000 mbps, prbs31; vih = 1 v, vil = 0 v 09530-189 200ps/div c1 200mv/di v figure 98. driver eye diagram, 2000 mbps, prbs31; vih = 2 v, vil = 0 v
adate318 rev. 0 | page 46 of 80 09530-195 ?0.2 ?0.6 ?0.4 ?0.8 0.4 0.6 0.8 0.2 0 0 5 time (s) 10 voltage (v) 20 15 vih to high-z vil to high-z figure 99. drive to/from high-z transition, vih = 1 v, vil = ?1 v, 50 termination 09530-210 20 ?20 ?100 0 ?40 ?60 ?80 80 100 60 40 05 time (ns) voltage (mv) 15 20 10 vil to iol vil to ioh vih to iol vih to ioh iol to vil iol to vih ioh to vil ioh to vih figure 100. drive to/from active lo ad transient, vil = vih = 0 v, ioh = iol = 0 v 09530-211 10 ?10 ?50 0 ?20 ?30 ?40 40 50 30 20 05 time (ns) voltage (mv) 15 20 25 30 35 40 45 50 10 vil to hiz vih to hiz hiz to vil hiz to vih figure 101. drive to/from high-z transient, vil = vih = 0 v, 50 termination 09530-197 ?0.02 0.08 0.06 0.04 0.02 ?0.04 0.12 0.14 0.16 0 0.10 0 2 time (ns) 4 voltage (v) 20 6 8 10 12 14 16 18 clc0 clc3 clc7 figure 102. driver 0.2 v response vs. clc settings 09530-198 ?0.1 0.4 0.3 0.2 0.1 ?0.2 0.6 0.7 0.8 0 0.5 0 2 time (s) 4 voltage (v) 20 6 8 10 12 14 16 18 clc0 clc3 clc7 figure 103. driver 1 v response vs. clc settings 09530-199 1.0 0.5 ?0.5 1.5 2.0 0 0 2 time (ns) 4 voltage (v) 20 6 8 10 12 14 16 18 clc0 clc3 clc7 figure 104. driver 3 v response vs. clc settings
adate318 rev. 0 | page 47 of 80 09530-200 4 3 2 1 ?1 5 6 0 0 10 time (s) voltage (v) 60 20 30 40 50 rise fall figure 105. ppmu transient response, fi range a, full -scale transition, uncalibrated, c load = 200 pf, r load = 120 09530-201 1.0 0.5 ?0.5 1.5 2.0 0 0 5 time (s) voltage (v) 30 10 15 20 25 rise fall figure 106. ppmu transient response , fi range b, full-scale transition, uncalibrated, c load = 200 pf, r load = 1.5 k 09530-202 1.0 0.5 ?0.5 1.5 2.0 0 010 time (s) voltage (v) 60 20 30 40 50 rise fall figure 107. ppmu transient response, fi range c, full-scale transition, uncalibrated, c load = 200 pf, r load = 15 k 09530-203 4 3 0 5 6 2 1 0 10 time (s) voltage (v) 60 20 30 40 50 rise fall figure 108. ppmu transient response, fv range a, 0 v to 5 v, uncalibrated, c load = 200 pf 09530-204 0.3 0.1 0.2 0 0.6 0.5 0.4 0 2 time (s) 4 voltage (v) 81 6 0 rise fall figure 109. ppmu transient response, fv range a, 0 v to 0.5 v, uncalibrated, c load = 200 pf 09530-205 0.3 0.1 ?0.1 0.2 0 0.6 0.7 0.5 0.4 05 time (s) voltage (v) 15 20 10 rise fall figure 110. ppmu transient response, fv range c, 0 v to 0.5 v, uncalibrated, c load = 200 pf
adate318 rev. 0 | page 48 of 80 0 09530-207 0.3 0.1 ?0.1 0.2 0 0.6 0.7 0.5 0.4 01 0 time (s) voltage (v) 30 40 20 rise fall 09530-206 0.3 0.1 0.2 0 0.6 0.5 0.4 024 time (s) voltage (v) 81 6 rise fall figure 111. ppmu transient response, fv range a, 0 v to 0.5 v, uncalibrated, c load = 2000 pf figure 112. ppmu transient response, fv range c, 0 v to 0.5 v, uncalibrated, c load = 2000 pf
adate318 rev. 0 | page 49 of 80 spi interconnect details 09530-003 adate318 (chip x) sclk sdi sdo busy cs csn adate318 (chip 1) sclk sdi sdo busy cs cs1 adate318 (chip 0) sclk sdi sdo busy cs cs0 notes 1. x 4. sclk cs[3:0] sdi sdo busy x . . . . . . . . . . . . figure 113. multiple spi with shared sdo line
adate318 rev. 0 | page 50 of 80 use of the spi busy pin after any valid spi instruction is written to the adate318, the busy pin becomes asserted to indicate a busy status of the dac update and calibration engines. the busy pin is an open drain type output capable of sinking a minimum of 5 ma from the vcc supply. because it is an open drain type output, it can be wire-ored in common with many other similar open drain devices. in such cases, it is the users responsibility either to determine which device is indicating the busy state or, alter- natively, to wait until all devices on the shared line become not busy. it is recommended that the busy pin be tied to vcc with an external 1 k pull-up. it is not a requirement to wait for release of busy prior to a subsequent assertion of the cs pin. this is not the purpose of the busy pin. as long as the minimum number of sclk cycles following the previous release of cs is met according to the t csam parameter, the cs pin can be asserted again for a subsequent spi operation. with the one exception of recovery from a reset request (either by hardware assertion of the rst pin or a sofware setting of the internal spi_reset control bit), there is no scenario in normal operation of the adate318 in which the user must wait for release of busy prior to asserting the cs for another spi operation. the only requirement on the assertion of cs is that the t csam parameter be defined as in and . figure 4 table 13 it is very important, however, that the sclk continue to operate for as long as the busy pin state remains active. this minimum period of time is defined by the t busw parameter (see , , , and ). if the sclk does not remain active for at least the time specified by the t busw parameter, oper- ations pending to the internal processor may not fully complete or, worse, they may complete in an incorrect fashion. in either case, a temporary malfunction of the adate318 may occur. figure 4 figure 6 figure 7 table 18 after the adate318 releases the busy pin, the sclk may again be stopped to prevent unwanted digital noise from coupling into the analog levels during normal operation of the pin electronics functions. in every case (with no exception for reset recovery), it is the purpose of the busy pin to notify the external test processor that it is again safe to stop the sclk signal to the adate318. running the sclk for extra periods when busy is not active is never a problem except for the possibility of adding unwanted digital switching noise to the analog pin electronics circuitry as already noted. while the length of the busy period (t busw ) is variable depending on the particular preceding spi instruction, it is nevertheless deterministic. the parameter t busw depends only on factors such as whether the previous instruction involved a write to one or more dac addresses and, if so, then how many channels were involved and whether or not the calibration function was enabled. describes the precise length of the t busw period in units of rising edge sclk cycles for each possible spi instruction scenario as well as recovery from a hard table 1 8 rst reset. because t busw is deterministic, it is therefore possible to predict in advance the minimum number of rising edge sclk cycles required to complete any given spi instruction. this makes it possible to operate the adate318 without a need to monitor the state of the busy pin. for applications in which it is neither possible nor desireable to monitor the pin, it is acceptable to use the information in to guarantee that the minimum number of cycles is provided in lieu of monitoring table 18 busy following release of cs or reset. all dac addresses have been assigned to the contiguous address block from 0x00 through 0x0f; therefore, it is possible to decode this information within the external test processor to provide a software indication that extra sclk cycles may be required according to the scenarios listed in . all other operations not involving these addresses require only the standard number of clock cycles determined by t csam . as stated above, however, it is extremely important to honor the minimum number of required rising edge sclk cycles as defined by t busw following the release of table 18 cs for each of the spi instruction scenarios listed in to ensure proper operation of the adate318. table 18 table 18. busy minimum sclk cycle requirements spi instruction type calibration engine 1 maximum t busw (sclk cycles) following the release of the asynch ronous reset pin (hardware reset) x 64 following assertion of the spi_reset control bit (software reset) x 64 no operation (nop) instruction x 3 read request to any valid adate318 address and/or channel (0x00 C 0x7f) x 3 single/double channel write request to any valid adate318 address 0x10 x 3 single channel write request to any dac (addr 0x01 C addr 0x0e) disabled 10 double channel write request to any dac (addr 0x01 C addr 0x0e) disabled 16 single channel write request to any dac (addr 0x01 C addr 0x0e) enabled 20 double channel write request to any dac (addr 0x01 C addr 0x0e) enabled 26 1 x = dont care.
adate318 rev. 0 | page 51 of 80 reset sequence and the rst pin the internal state of the adate318 is indeterminate following power-up. for this reason, it is necessary to perform a complete reset sequence once the power supplies have stabilized. further, the rst pin must be held in the asserted state before and during the power-up sequence and released only after all power supplies are known to be stable. the adate318 has an active low pin ( rst ) that asynchron- ously starts a reset sequence. a soft reset sequence can also be initiated under spi software control by writing to the spi_reset bit in the spi control register (spi 0x12[0] (see )). in the case of a soft reset, the sequence begins on the first rising edge of sclk following the release of figure 13 cs , subject to the normal setup and hold times. certain actions take place immediately upon initiation of the reset request, whereas other actions require sclk. the following asynchronous actions take place as soon as a reset request is detected, whether or not sclk is active: ? assert busy pin ? force all control registers to the default reset state as defined by control register definitions ? clear all calibration registers to the default reset state as defined by calibration register definitions ? override all dac output voltages and force analog levels to v dutgnd ? disable dcls and ppmus; open system pmu switches ? soft connect the dut0 and dut1 pins to v dutgnd (see figure 114 ) t he part remains in this static reset state indefinitely until the clocked portion of the sequence begins with either the first rising edge of sclk following the release of rst (asynch- ronous reset) or the second rising edge of sclk following the release of cs (soft reset). no matter how the reset sequence is initiated, the clocked portion of the reset sequence requires 64 sclk cycles to run to completion, and the busy pin remains asserted until these clock cycles have been received. the following actions take place during the clocked portion of the reset sequence: ? complete internal spi controller initialization ? write the appropriate values to specific dac x 2 registers (see table 19 ) ? enable the thermal alarm with a 100c threshold; disable ppmu and the overvoltage detect (ovd) alarms the 64 th rising edge of sclk releases busy and starts a self- timed dac deglitch period of approximately 3 s. dac voltages begin to change once the deglitch circuits have timed out, and they then require an additional 10 s to settle to their final values. thus, a full reset sequence requires approximately 15 s, comprising 1.28 s (64 cycles 20 ns) for the reset state machine, 3 s for dac deglitch, and another 10 s for settling. 09530-010 driver dutgnd dutx comparators 50 ? 10k? clamps to ppmu load dut pulldownx addr 0x19[7] dut pull-down switch defaults to a closed state immediately following an assert of rst (for hard reset) or at the first rising edge of sclk following the spi cs (for soft reset). see dcl control register 0x19[7]. figure 114. dutx to vdutgnd soft connect detail
adate318 rev. 0 | page 52 of 80 spi register definitions and memory map 09530-011 d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 c 1 c 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 r/w 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 spi word index 123 456789 spi clock index ch[1:0] channel select 00 = nop 01 = read/write channel 0 10 = read/write channel 1 11 = read nop 11 = write channel 0 and 1 addr[6:0] address field data[15:0] data field r/w read/write select 0 = read: 1 = write: the contents of register specified by addr[6:0] and ch[1:0] are shifted out on the sdo pin during the next spi instruction cycle. data[15:0] is written to the register specified by addr[6:0] and ch[1:0]. figure 115. spi word definition table 19. spi register memory map ch[1:0] 1, 2 addr[6:0] r /w 1 data[15:0] 1, 3 register description reset value 1 xx 0x00 x xxxx no operation (nop) xxxx cc 0x01 r/w dddd vih dac level (reset value = 0.0 v) 0x4000 cc 0x02 r/w dddd vit/vcom dac level (reset value = 0.0 v) 0x4000 cc 0x03 r/w dddd vil dac level (reset value = 0.0 v) 0x4000 cc 0x04 r/w dddd voh dac level (reset value = +0.5 v)) 0x4ccc cc 0x05 r/w dddd vol dac level (reset value = ?0.5 v) 0x3333 cc 0x06 r/w dddd vch dac level (reset value = +7.5 v) 0xffff cc 0x07 r/w dddd vcl dac level (reset value = ?2.5 v) 0x0000 cc 0x08 r/w dddd vioh dac level (reset value = 50 a) 0x4040 cc 0x09 r/w dddd viol dac level (reset value = 50 a) 0x4040 cc 0x0a r/w dddd ppmu dac level (reset value = 0.0 v) 0x4000 01 0x0b r/w dddd vhh dac level (reset value = 0.0 v) 0x2666 01 0x0c r/w dddd ovdh dac level (reset value = +7.5 v) 0xffff 01 0x0d r/w dddd ovdl dac level (reset value = ?2.5 v) 0x0000 01 0x0e r/w dddd spare dac level (reset value = 0.0 v) 0x4000 xx 0x0f x xxxx reserved xxxx xx 0x10 x xxxx no operation (nop) xxxx cc 0x11 r/w dddd dac control register 0x0000 01 0x12 r/w dddd spi control register 0x0000 xx 0x13 to 0x17 x xxxx reserved xxxx 01 0x18 r/w dddd vhh control register 0x0000 cc 0x19 r/w dddd dcl control register 0x0080 cc 0x1a r/w dddd ppmu control register 0x0000 cc 0x1b r/w dddd ppmu meas control register 0x0000 cc 0x1c r/w dddd cmp control register 0x07fe cc 0x1d r/w dddd alarm mask register 0x0045 cc 0x1e r dddd alarm state register 0x0000 cc 0x1f r/w dddd clc control register 0x0000 xx 0x20 x xxxx no operation (nop) xxxx cc 0x21 r/w dddd vih (driver) m-coefficient 0xffff cc 0x22 r/w dddd vit (driver) m-coefficient 0xffff cc 0x23 r/w dddd vil (driver) m-coefficient 0xffff cc 0x24 r/w dddd voh (normal window comparator) m-coefficient 0xffff
adate318 rev. 0 | page 53 of 80 ch[1:0] 1 , 2 addr[6:0] r /w 1 data[15:0] 1 , 3 register description reset value 1 cc 0x25 r/w dddd vol (normal window comparator) m-coefficient 0xffff cc 0x26 r/w dddd vch (reflection clamp) m-coefficient 0xffff cc 0x27 r/w dddd vcl (reflection clamp) m-coefficient 0xffff cc 0x28 r/w dddd vioh (active load) m-coefficient 0xffff cc 0x29 r/w dddd viol (active load) m-coefficient 0xffff cc 0x2a r/w dddd ppmu (ppmu force-voltage) m-coefficient 0xffff 01 0x2b r/w dddd vhh (hvout) m-coefficient 0xffff 01 0x2c r/w dddd ovdh (overvoltage) m-coefficient 0xffff 01 0x2d r/w dddd ovdl (overvoltage) m-coefficient 0xffff 01 0x2e r/w dddd spare dac m-coefficient 0xffff xx 0x2f x xxxx reserved xxxx xx 0x30 x xxxx no operation (nop) xxxx cc 0x31 r/w dddd vih (driver) c-coefficient 0x8000 cc 0x32 r/w dddd vit (driver) c-coefficient 0x8000 cc 0x33 r/w dddd vil (driver) c-coefficient 0x8000 cc 0x34 r/w dddd voh (normal window comparator) c-coefficient 0x8000 cc 0x35 r/w dddd vol (normal window comparator) c-coefficient 0x8000 cc 0x36 r/w dddd vch (reflection clamp) c-coefficient 0x8000 cc 0x37 r/w dddd vcl (reflection clamp) c-coefficient 0x8000 cc 0x38 r/w dddd vioh (active load) c-coefficient 0x8000 cc 0x39 r/w dddd viol (active load) c-coefficient 0x8000 cc 0x3a r/w dddd ppmu (ppmu force voltage) c-coefficient 0x8000 01 0x3b r/w dddd vhh (hvout ) c-coefficient 0x8000 01 0x3c r/w dddd ovdh (overvoltage) c-coefficient 0x8000 01 0x3d r/w dddd ovdl (overvoltage) c-coefficient 0x8000 01 0x3e r/w dddd spare dac c-coefficient 0x8000 xx 0x3f x xxxx reserved xxxx xx 0x40 x xxxx no operation (nop) xxxx 01 0x41 r/w dddd vih (hvout) m-coefficient 0xffff cc 0x42 r/w dddd vcom (active load) m-coefficient 0xffff 01 0x43 r/w dddd vil (hvout) m-coefficient 0xffff 01 0x44 r/w dddd voh (differential comparator) m-coefficient 0xffff cc 0x45 r/w dddd voh (ppmu measure voltage) m-coefficient 0xffff cc 0x46 r/w dddd voh (ppmu measure current, range a) m-coefficient 0xffff cc 0x47 r/w dddd voh (ppmu measure current range b) m-coefficient 0xffff cc 0x48 r/w dddd voh (ppmu measure current, range c) m-coefficient 0xffff cc 0x49 r/w dddd voh (ppmu measure current, range d) m-coefficient 0xffff cc 0x4a r/w dddd voh (ppmu measure current, range e) m-coefficient 0xffff 01 0x4b r/w dddd vol (differential comparator) m-coefficient 0xffff cc 0x4c r/w dddd vol (ppmu measur e voltage) m-coefficient 0xffff cc 0x4d r/w dddd vol (ppmu measure current, range a) m-coefficient 0xffff cc 0x4e r/w dddd vol (ppmu measure curr ent, range b) m-coefficient 0xffff cc 0x4f r/w dddd vol (ppmu measure current, range c) m-coefficient 0xffff cc 0x50 r/w dddd vol (ppmu measure current, range d) m-coefficient 0xffff cc 0x51 r/w dddd vol (ppmu measure current, range e) m-coefficient 0xffff cc 0x52 r/w dddd vch (ppmu) m-coefficient 0xffff cc 0x53 r/w dddd vcl (ppmu) m-coefficient 0xffff cc 0x54 r/w dddd ppmu force current, range a m-coefficient 0xffff cc 0x55 r/w dddd ppmu force current, range b m-coefficient 0xffff cc 0x56 r/w dddd ppmu force current, range c m-coefficient 0xffff cc 0x57 r/w dddd ppmu force current range d m-coefficient 0xffff cc 0x58 r/w dddd ppmu force current, range e m-coefficient 0xffff 01 0x59 r/w dddd vih (hvout ) c-coefficient 0x8000 cc 0x5a r/w dddd vcom (active load) c-coefficient 0x8000 01 0x5b r/w dddd vil (hvout) c-coefficient 0x8000 01 0x5c r/w dddd voh (differential comparator) c-coefficient 0x8000 cc 0x5d r/w dddd voh (ppmu measure voltage) c-coefficient 0x8000
adate318 rev. 0 | page 54 of 80 ch[1:0] 1 , 2 addr[6:0] r /w 1 data[15:0] 1 , 3 register description reset value 1 cc 0x5e r/w dddd voh (ppmu measure current) c-coefficient 0x8000 xx 0x5f to 0x62 x xxxx reserved xxxx 01 0x63 r/w dddd vol (differential co mparator) c-coefficient 0x8000 cc 0x64 r/w dddd vol (ppmu measure voltage) c-coefficient 0x8000 cc 0x65 r/w dddd vol (ppmu measure current) c-coefficient 0x8000 xx 0x66 to 0x69 x xxxx reserved xxxx cc 0x6a r/w dddd vch (ppmu) c-coefficient 0x8000 cc 0x6b r/w dddd vcl (ppmu) c-coefficient 0x8000 cc 0x6c r/w dddd ppmu force current c-coefficient 0x8000 xx 0x6d to 0x70 x xxxx reserved xxxx 1 x = dont care. 2 cc corresponds to the channel address bits and indicates that there is dedicated register space for each channel. 3 dddd stands for data.
adate318 rev. 0 | page 55 of 80 control register details reserved bits in any register are undefined. in some cases, a physical (but unused) memory bit may be present, in other cases not. write operations have no effect. read operations result in meaningless but deterministic data. any spi read operation from any reserved bit or register results in an unknown but deterministic readback value. any spi write operation to a control bit or control register defined only on channel 0 must be addressed to at least channel 0. any such write that is addressed only to channel 1 is ignored. further, any such write that is addressed to both channel 0 and channel 1 (as a multichannel write) proceeds as if the write were addressed only to channel 0. the data addressed to the undefined channel 1 control bit or control register is ignored. 09530-012 reserved[15:3] reserved dac_load[2] dac load soft pin, self-resetting, channel 0/channel 1 [0] = default state of the dac_load soft pin 1 = begin dac load operation (pulse, self-clear to zero) a write to this bit parallel updates all dacs of channel x with previously buffered data assuming that the dac_load_mode control bit of channel x is not set to write dac immediate mode. this bit automatically self-clears. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index dac_cal_enable[0] dac calibration engine enable, channel 0 only [0] = calibration engine is disabled 1 = calibration engine is enabled when dac calibration is enabled, each write to a valid dac address results in a subsequent multiply and accumulate (mac) operation to the data for the respective dac using calibration data contained in the appropriate m- and c- coefficient registers. when the calibration engine is disabled, data written to a valid dac address is not modified by the on-chip calibration coefficients. dac_load_mode[1] dac load mode, channel 0/channel 1 [0] = write dac immediate mode. 1 = write dac deferred mode. in write dac immediate mode, each respective dac is updated immediately subsequent to a valid spi write instruction to that dac address. in write dac deferred mode, each valid spi write to a dac address is buffered, and dacs are only updated following assertion of the dac_load soft pin. in this mode, all analog dac data for either or both channels can be updated in parallel. figure 116. dac control register (addr = 0x11)
adate318 rev. 0 | page 56 of 80 09530-013 reserved[15:2] reserved spi_reset[0] spi software reset, channel 0 only [0] = default setting, no action is taken until a 1 is written. 1 = reset (pulse, self-clear to zero). following a write to set this bit, the adate318 begins a full reset sequence just as if the rst pin had been a sserted asynchronously. following reset this bit self-clears to the default 0 condition. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index spi_sdo_hiz[1] spi serial data output pin, high-z control, channel 0 only [0] = sdo pin is always active, independent of the cs input. 1 = sdo pin is active only when cs is active, otherwise high-z. figure 117. spi control register (addr = 0x12) 09530-014 reserved[15:1] reserved v hh_enable[0] v hh (hvout) enable, channel 0 only [0] = hvout pin is disabled. 1 = hvout pin is enabled. w hen vhh mode is enabled, the hvout pin is set to the levels a ccording to the vhh and vih/vil driver truth table (table 25). w hen vhh mode is disabled, the impedance of the hvout pin is approximately 50 ? to vdutgnd. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index figure 118. vhh control register (addr = 0x18) active truth table
adate318 rev. 0 | page 57 of 80 09530-015 reserved[15:8] reserved drive_vt_hiz_x[6] driver vt/hiz mode select, channel 0/channel 1 [0] = driver goes to high-z state when rcvx = 1. 1 = driver goes to vit state when rcvx = 1. w hen drv_vt_hiz is asserted, the driver on channel x assumes the vit level on assertion of the rcvx high speed input in a ccordance with the driver truth table. this control bit is subordinate to the dcl_enable and force_drive control bits. load_enable_x[5] a ctive load enable, channel 0/channel 1 [0] = active load is disabled and powered down. 1 = active load is enabled. w hen load_enable is asserted, the active load on channel x is enabled a nd connects to the dutx pin on assertion of the rcvn high speed input in accordance with the active load truth table. this control bit is subordinate to the dcl_enable and force_load control bits but takes precedence over the rcvn high speed inputs. force_drive_state_x[4:3] driver state when force_drive, channel 0/channel 1 [00] = force drive vil state. 01 = force drive vih state. 10 = force drive high-z state. 11 = force drive vit state. w hen the force_drive control bit is active, the driver on channel x a ssumes the indicated state in accordance with the driver truth table. force_load_x[2] force active load to active on state, channel 0/channel 1 [0] = active load responds to rcvx. 1 = force active on state. w hen force_load is asserted, the active load on channel x assumes the active on state and is connected to the dutx pin in accordance with the active load truth table. this control bit is subordinate to the dcl_enable control bit but takes precedence over both the load_enable and drv_vt_hiz control bits, as well as the rcvx inputs. this bit does not force selection of vcom calibration constants. force_drive_x[1] force driver to force_state, channel 0/channel 1 [0] = driver responds to datx and rcvx. 1 = force driver state to force_state. w hen force_drive is asserted, the driver on channel x assumes the state indicated by force_state in accordance with the driver truth table. this control bit is subordinate to the dcl_enable control bit but takes precedence over drv_vt_hiz, as well as the datx and rcvx inputs. this bit does not force selection of vch and vcl calibration constants nor does it force selection of vit calibration constants. dcl_enable_x[0] enable dcl on channel 0/channel 1 [0] = dcl is disabled (low leakage mode). 1 = dcl is enabled. w hen dcl_enable is not asserted, the driver, comparator, and active load on channel x assume the low leakage state in accordance with driver and a ctive load truth tables. this control bit takes precedence over all other control bits in the dcl control register except for dut_pulldown. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index dut_pulldown_x[7] dutx pin 10k soft pull-down, channel 0/channel 1 0 = hvout pin is disabled. [1] w hen dut_pulldown is asserted, the dutx pin on channel x has a 10k ? pull-down to dutgnd. this control bit is a synchronously set at the beginning of any reset operation, a nd it remains set until cleared by the user. this control bit does not depend on other control bits in this register. = dutx pin has 10k ? pull-down to dutgnd. figure 119. dcl control register (addr = 0x19)
adate318 rev. 0 | page 58 of 80 09530-016 ppmu_power_x[15] ppmu power, channel 0/channel 1 [0] = ppmu power off. 1 = ppmu power on. when ppmu_power_x[15] = 1, the nwc and dmc hysteresis is forced to a maximum, but the hysteresis register values are left unchanged. pmu_s_enable_x[11] pmu sense input enable, channel 0/channel 1 [0] = pmu sense input switch open. 1 = pmu sense input switch closed. ppmu_clamp_enable_x[9] ppmu clamp enable, channel 0/channel 1 [0] = ppmu clamps disabled. 1 = ppmu clamps enabled. ppmu_meas_vi_x[5] ppmu measure v or measure i, channel 0/channel 1 [0] = ppmu measure v mode. 1 = ppmu measure i mode. ppmu_range_x[3:1] ppmu range, channel 0/channel 1 [0xx] = ppmu range e (2a). 100 = ppmu range d (10a). 101 = ppmu range c (100a). 110 = ppmu range b (1ma). 111 = ppmu range a (40ma). ppmu_force_vi_x[4] ppmu force v or force i, channel 0/channel 1 [0] = ppmu force v mode. 1 = ppmu force i mode. ppmu_enable_x[0] ppmu enable, channel 0/channel 1 [0] = ppmu full power standby. 1 = ppmu active. ppmu_sense_path_x[8] ppmu sense path, channel 0/channel 1 [0] = ppmu internal sense path. 1 = ppmu external sense path. ppmu_input_sel_x[7:6] ppmu input select, channel 0/channel 1 [00] = ppmu input from dutgnd. 01 = ppmu input from dutgnd + 2.5v. 1x reserved[14:12] reserved reserved d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index = ppmu input from dac ppmu level. figure 120. ppmu control register (addr = 0x1a)
adate318 rev. 0 | page 59 of 80 09530-017 reserved[15:3] reserved ppmu_meas_sel_x[2:1] ppmu analog measure out pin select, channel 0/channel 1 [x0] = ppmu channel x to ppmu_measx output pin. x1 = channel 0: temperature sensor output (therm). channel 1: temperature sensor gnd reference. ppmu_meas_enable_x[0] ppmu analog measure out pin enable, channel 0/channel 1 [0] = ppmu measure out pin on channel x is disabled, high-z. 1 = ppmu measure out pin on channel x is enabled. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index figure 121. ppmu meas control register (addr = 0x1b) 09530-018 reserved[15:11] reserved nwc_hyst_x[10:6] normal window comparator hysteresis value, channel 0/channel 1 0x00 = disable hysteresis. 0x01 = enable minimum hysteresis. [0x1f] w hen set to 0x00, the normal window comparator on channel x has no hysteresis added to the input stage. when set to a value other than 0x00, hysteresis is added and the amount is controlled by the value in this register. w hen addr 0x1a ppmu _power_x[15] = 1, the nwc hysteresis is forced to a maximum, but the hysteresis register value is left unchanged. dmc_hyst[5:1] differential comparator hysteresis value, channel 0 only 0x00 = disable hysteresis. 0x01 = enable minimum hysteresis. [0x1f] w hen set to 0x00, the differential comparator on channel 0 has no hysteresis added to the input stage. when set to a value other than 0x00, hysteresis is added and the amount is controlled by the value in this register. w hen addr 0x1a ppmu _power_x[15] = 1, the dmc hysteresis is forced to a maximum, but the hysteresis register value is left unchanged. dmc_enable[0] differential mode comparator enable, channel 0 only [0] = disable differential mode comparator. 1 = enable differential mode comparator. w hen dmc_enable is asserted, the normal window comparator on channel 0 is disabled, the differential mode comparator on channel 0 is enabled, and its outputs goes to the cmph0 and cmpl0 high speed output pins. the operation of the normal window comparator on channel 1 is not affected. this control bit exists a t addr 0x1c channel 0 only. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index = enable maximum hysteresis. = enable maximum hysteresis. figure 122. cmp control register (addr = 0x1c)
adate318 rev. 0 | page 60 of 80 09530-019 reserved[15:7] reserved therm_alarm_mask[3] thermal alarm mask bit, channel 0 only [0] = thermal alarm enabled. 1 w hen the thermal alarm is enabled, a temperature sensor reading a bove the threshold specified by therm_alarm_thresh a sserts and latches the alarm open drain output pin. ppmu_alarm_mask_x[2] ppmu clamp alarm mask, channel 0/channel 1 0 [1] = ppmu clamp alarm disabled. w hen the ppmu clamp is enabled, a clamp condition on channel x ppmu clamps asserts and latches the alarm open drain output pin. the ppmu clamp levels are defined by the vcl and vch dac registers. ovd_alarm_mask_n[0] overvoltage detector alarm mask, channel 0/channel 1 0 = overvoltage alarm enabled. [1] w hen the ovd alarm is enabled, an overvoltage fault condition on dutx asserts and latches the alarm open drain output pin. the overvoltage thresholds are defined by the ovdh and ovdl dac regisiters. reserved[1] reserved d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index therm_alarm_thresh[6:4] thermal alarm threshold, channel 0 only 000 = 0c (for test use only) 001 = 25c 010 = 50c 011 = 75c [100] 101 = 125 c 110 = 150 c 111 = 175 c = 100c = overvoltage alarm disabled. = ppmu clamp alarm enabled. = thermal alarm disabled. figure 123. alarm mask register (addr = 0x1d)
adate318 rev. 0 | page 61 of 80 09530-020 reserved[15:4] reserved ppmu_alarm_flag_x[2] ppmu clamp alarm flag, channel 0/channel 1 [0] = ppmu clamp condition not detected. 1 = ppmu clamp condition detected. w hen the ppmu_alarm_flag bit is set, a ppmu clamp condition was detected on channel x according to the thresholds set in the v ch and vcl clamp registers. this flag is subordinate to the ppmu_alarm_mask_x control bit, and it automatically resets a fter any read from the alarm state register. ovdh_alarm_flag_x[1] over voltage alarm flag, channel 0/channel 1 [0] = over voltage fault not detected. 1 = over voltage fault detected. w hen ovdh_alarm_flag is set, an over voltage fault condition w as detected on channel x dutx pin according to the threshold set in the ovdh dac register. this flag is subordinate to the ovd_alarm_mask_x control bit, and it is automatically reset a fter any read from the alarm state register. ovdl_alarm_flag_x[0] under voltage alarm flag, channel 0/channel 1 [0] = under voltage fault not detected. 1 = under voltage fault detected. w hen ovdl_alarm_flag is set, an under voltage fault condition w as detected on channel x dutx pin according to the threshold set in the ovdl dac register. this flag is subordinate to the ovd_alarm_mask_x control bit, and it is automatically reset a fter any read from the alarm state register. d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index therm_alarm_flag[3] thermal alarm flag, channel 0 only [0] = thermal fault not detected. 1 = thermal fault detected. w hen the therm_alarm_flag bit is set, a fault was detected on the die according to the thermal threshold set in the therm_alarm_thresh register. this flag is subordinate to the therm_alarm_mask control bit, and it is automatically reset after any read from the alarm state register. figure 124. alarm state regist er (addr = 0x1e) (read only)
adate318 rev. 0 | page 62 of 80 09530-021 reserved[12:11] reserved reserved[7:6] reserved reserved[2:0] reserved d 1 d 0 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 24 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 data-word index spi clock index drv_clc_x[15:13] driver cable loss compensation, channel 0/channel 1 [000] = disable driver clc. 001 = enable driver minimum clc. 111 = enable driver maximum clc. when set to 0x00, the driver on channel x has zero cable loss compensation (clc) added to its output characteristic. when set to a value other than 0x00, cable loss compensation pre-emphasis is added and the percentage is controlled by the register value. nwc_clc_x[10:8] normal window comparator cable loss compensation, channel 0/channel 1 [000] = disable nwc clc. 001 = enable nwc minimum clc. 111 = enable nwc maximum clc. when set to 0x00, the normal window comparator (nwc) on channel x has no cable loss compensation (clc) added to the input added to the input waveform characteristic. when set to a value other than 0x00, pre-emphasis is added and the percentage is controlled by the value in this register. dmc_clc[5:3] differential mode comparator cable loss compensation, channel 0 only [000] = disable dmc clc. 001 = enable dmc minimum clc. 111 = enable dmc maximum clc. when set to 0x00, the differential mode comparator (on channel 0 only) has no cable loss compensation (clc) added to the input waveform characteristic. when set to a value other than 0x00, pre-emphasis is added and the percentage is controlled by the value in this register. figure 125. clc control register (addr = 0x1f)
adate318 rev. 0 | page 63 of 80 level setting dacs dac update modes the adate318 provides 24- 16-bit integrated level setting dacs organized as two channel banks of 12 dacs each. the detailed mapping of the dac register to pin electronics function is shown in table 19 . each dac can be programmed by writing data to the respective spi register address and channel. the adate318 provides two methods for updating analog dac levels: dac immediate update mode and dac deferred update mode. at release of the cs pin associated with any valid spi write to a dac address, the update of analog levels may start immediately , or it can be deferred, depending on the state of the dac_load_mode control bits in the dac control register (spi addr 0x11[1] (see )). the dac update mode can be selected independently for each channel bank. 1 figure 116 if the dac_load_mode control bit for a given channel bank is cleared, the dacs assigned to that channel are then in the dac immediate update mode. writing to any dac of that channel causes the corresponding analog level to be updated immediately following the associated release of cs . because all analog levels are updated on a per-channel basis, any previously pending dac writes queued to the channel (while in deferred update mode) are also updated at this time. this situation can arise if dac writes are queued to the channel while in deferred update mode, and the dac_load_mode bit is subsequently changed to immediate update mode before the analog levels are updated by writing to the respective dac_load soft pin. the queued data is not lost. note that writing to the dac_load soft pin has no effect in immediate update mode. if the dac_load_mode control bit for a given channel is set, the dacs assigned to that channel are in the deferred update mode. writing to any dac of that channel only queues the dac data into that channel. the analog update of queued dac levels is deferred until the respective dac_load soft pin is set (spi addr 0x11[2] (see figure 116 )). the dac deferred update mode, in conjunction with the respective dac_load soft pin, provides the means to queue all dac level writes to a given channel bank before synchronously updating the analog levels with a single spi command. certain pin electronics functions, such as vhh, ovdh, ovdl, and the spare dac, do not fit neatly within a particular channel bank. however, they must be updated as a part of the channel bank to which they are assigned as shown in table 19 . the adate318 provides a feature in which a single spi write operation can address two channels at one time (see figure 115 ). this feature makes possible a scenario in which a spi write 1 initiation of the analog level update sequence (and triggering of the on-chip deglitch circuit) actually begins four sclk cycles following the associated release of the cs pin. for the purpose of this discussion, it is assumed to start coincident with the release of cs . operation can address corresponding dacs on both channels at the same time even though the channels may be configured with different dac update modes. in such a case, the part behaves as expected. for example, if both channels are in immediate update mode, the update of analog levels of both channel banks begins after the associated release of the cs pin. if both channels are in deferred update mode, the update of analog levels is deferred for both channels until the corres- ponding dac_load bits are set. if one channel is in deferred update mode and the other channel is in immediate update mode, the former channel defers analog updates until the corresponding dac_load bit is written, and the latter channel begins analog updates immediately after the associated release of the cs pin. an on-chip deglitch circuit with a period of approximately 3 s is provided to prevent dac-to-dac crosstalk whenever an analog update is processed. only one deglitch circuit is provided per chip, and it must operate over all physical dacs (both channels) at the same time. the deglitch circuit can be retriggered when an analog levels update is initiated before a previous update operation has completed. in the case of a dual- channel immediate mode dac write using a single spi command, the deglitch circuit is triggered once after data is loaded into both dac channels. analog transitions at the dac outputs do not begin until the deglitch circuit has timed out, and final settling to full precision requires an additional 7 s beyond the end of the 3 s deglitch interval. total settling time following release of the associated cs is approximately 10 s. note that prolonged and consecutive retriggering of the deglitch circuit by one channel may cause the apparent settling time of analog levels on the other channel to be much longer than the specified 10 s. a typical dac update sequence is illustrated in figure 126 in which two immediate mode dac update commands are written in direct succession. this example illustrates what happens when a dac update command is written subsequent to a previous update command that has not yet finished its deglitch and settling sequence. recommended sequence for ovdh dac level addressing for correct ovdh addressing, first write data to the ovdh dac level at spi 0x0c at ch0. if in dac immediate mode, the ovdh data write must be followed by either a dac_load command to spi 0x11[2] at ch1 or a subsequent write to any other ch1 dac data address before the ovdh value will be updated. if in dac deferred mode, the ovdh dac level write must be followed by a dac_load command to spi 0x11[2] at ch1 (not ch0) before the analog ovdh value will be updated.
adate318 rev. 0 | page 64 of 80 09530-022 t spi 3s t dac note 1 note 1 0.5 lsb completion of 3s deglitch period retrigger of 3s deglitch period beginning of 3s deglitch period notes 1. dac deglitch period always begins four sclk cycles before release of busy. dac 23 dac 2 dac 1 dac 0 busy sdi cs sclk see table 18 write dac 0 write dac 1 see table 18 . . . . . . . . figure 126. spi dac write and settling time addressing m and c registers some dacs have pairs of m/c-coefficients that are controlled depending on other register status. table 20 details the specific register settings and register addresses for the different pairs (x = dont care). table 20. m- and c-register mapping spi address (channel) dac name functional (dac usage) description m- register c- register vhh_ enable 0x18[0] dmc_ enable 0x1c[0] load_ enablex 0x19[5] ppmu_ powerx 0x1a[15] ppmu_ meas_ vix 0x1a[5] ppmu_force _vix 0x1a[4] ppmu_ rangex (0x1a[3:1]) 0x0d[0] ovdl overvoltage detect low 0x2d[0] 0x3d[0] x x x x x x xxx 0x04[0] voh0 nwc high level, channel 0 0x24[0] 0x34[0] x 0 x 0 x x xxx dmc high level 0x44[0] 0x5c[0] x 1 x 0 x x xxx ppmu go/no-go mv high level, channel 0 0x45[0] 0x5d[0] x x x 1 0 x xxx ppmu go/no-go mi range a high level, channel 0 0x46[0] 0x5e[0] x x x 1 1 x 111 ppmu go/no-go mi range b high level, channel 0 0x47[0] 0x5e[0] x x x 1 1 x 110 ppmu go/no-go mi range c high level, channel 0 0x48[0] 0x5e[0] x x x 1 1 x 101 ppmu go/no-go mi range d high level, channel 0 0x49[0] 0x5e[0] x x x 1 1 x 100 ppmu go/no-go mi range e high level, channel 0 0x4a[0] 0x5e[0] x x x 1 1 x 0xx
adate318 rev. 0 | page 65 of 80 spi address (channel) dac name functional (dac usage) description m- register c- register vhh_ enable 0x18[0] dmc_ enable 0x1c[0] load_ enablex 0x19[5] ppmu_ powerx 0x1a[15] ppmu_ meas_ vix 0x1a[5] ppmu_force _vix 0x1a[4] ppmu_ rangex (0x1a[3:1]) 0x05[0] vol0 nwc low level, channel 0 0x25[0] 0x35[0] x 0 x 0 x x xxx dmc low level 0x4b[0] 0x63[0] x 1 x 0 x x xxx ppmu go/no-go mv low level, channel 0 0x4c[0] 0x64[0] x x x 1 0 x xxx ppmu go/no-go mi range a low level, channel 0 0x4d[0] 0x65[0] x x x 1 1 x 111 ppmu go/no-go mi range b low level, channel 0 0x4e[0] 0x65[0] x x x 1 1 x 110 ppmu go/no-go mi range c low level, channel 0 0x4f[0] 0x65[0] x x x 1 1 x 101 ppmu go/no-go mi range d low level, channel 0 0x50[0] 0x65[0] x x x 1 1 x 100 ppmu go/no-go mi range e low level, channel 0 0x51[0] 0x65[0] x x x 1 1 x 0xx 0x08[0] vioh0 load ioh level, channel 0 0x28[0] 0x38[0] x x x x x x xxx 0x09[0] viol0 load iol level, channel 0 0x29[0] 0x39[0] x x x x x x xxx 0x02[0] vit0/ vcom0 drive term level, channel 0 0x22[0] 0x32[0] x x 0 x x x xxx load commutation voltage, channel 0 0x42[0] 0x5a[0] x x 1 x x x xxx 0x01[0] vih0 drive high level, channel 0 0x21[0] 0x31[0] 0 x x x x x xxx hvout drive high level, channel 0 0x41[0] 0x59[0] 1 x x x x x xxx 0x03[0] vil0 drive low level, channel 0 0x23[0] 0x33[0] 0 x x x x x xxx hvout drive low level, channel 0 0x43[0] 0x5b[0] 1 x x x x x xxx 0x06[0] vch0 ref clamp high level, channel 0 0x26[0] 0x36[0] x x x 0 x x xxx ppmu clamp high level, channel 0 0x52[0] 0x6a[0] x x x 1 x x xxx 0x07[0] vcl0 ref clamp low level, channel 0 0x27[0] 0x37[0] x x x 0 x x xxx ppmu clamp low level, channel 0 0x53[0] 0x6b[0] x x x 1 x x xxx 0x0a[0] ppmu0 ppmu vin fv level, channel 0 0x2a[0] 0x3a[0] x x x x x 0 xxx ppmu vin fi range a level, channel 0 0x54[0] 0x6c[0] x x x x x 1 111 ppmu vin fi range b level, channel 0 0x55[0] 0x6c[0] x x x x x 1 110 ppmu vin fi range c level, channel 0 0x56[0] 0x6c[0] x x x x x 1 101 ppmu vin fi range d level, channel 0 0x57[0] 0x6c[0] x x x x x 1 100 ppmu vin fi range e level, channel 0 0x58[0] 0x6c[0] x x x x x 1 0xx 0x0b[0] vhh vhh level 0x2b[0] 0x3b[0] x x x x x x xxx 0x0c[0] ovdh overvoltage detect high 0x2c[0] 0x3c[0] x x x x x x xxx
adate318 rev. 0 | page 66 of 80 spi address (channel) dac name functional (dac usage) description m- register c- register vhh_ enable 0x18[0] dmc_ enable 0x1c[0] load_ enablex 0x19[5] ppmu_ powerx 0x1a[15] ppmu_ meas_ vix 0x1a[5] ppmu_force _vix 0x1a[4] ppmu_ rangex (0x1a[3:1]) 0x04[1] voh1 nwc high level, channel 1 0x24[1] 0x34[1] x x x 0 x x xxx ppmu go/no-go mv high level, channel 1 0x45[1] 0x5d[1] x x x 1 0 x xxx ppmu go/no-go mi range a high level, channel 1 0x46[1] 0x5e[1] x x x 1 1 x 111 ppmu go/no-go mi range b high level, channel 1 0x47[1] 0x5e[1] x x x 1 1 x 110 ppmu go/no-go mi range c high level, channel 1 0x48[1] 0x5e[1] x x x 1 1 x 101 ppmu go/no-go mi range d high level, channel 1 0x49[1] 0x5e[1] x x x 1 1 x 100 ppmu go/no-go mi range e high level, channel 1 0x4a[1] 0x5e[1] x x x 1 1 x 0xx 0x05[1] vol1 nwc low level, channel 1 0x25[1] 0x35[1] x x x 0 x x xxx ppmu go/no-go mv low level, channel 1 0x4c[1] 0x64[1] x x x 1 0 x xxx ppmu go/no-go mi range a low level, channel 1 0x4d[1] 0x65[1] x x x 1 1 x 111 ppmu go/no-go mi range b low level, channel 1 0x4e[1] 0x65[1] x x x 1 1 x 110 ppmu go/no-go mi range c low level, channel 1 0x4f[1] 0x65[1] x x x 1 1 x 101 ppmu go/no-go mi range d low level, channel 1 0x50[1] 0x65[1] x x x 1 1 x 100 ppmu go/no-go mi range e low level, channel 1 0x51[1] 0x65[1] x x x 1 1 x 0xx 0x08[1] vioh1 load ioh level, channel 1 0x28[1] 0x38[1] x x x x x x xxx 0x09[1] viol1 load iol level, channel 1 0x29[1] 0x39[1] x x x x x x xxx 0x02[1] vit1/ vcom1 drive term level, channel 0 0x22[1] 0x32[1] x x 0 x x x xxx load commutation voltage, channel 1 0x42[1] 0x5a[1] x x 1 x x x xxx 0x01[1] vih1 drive high level, channel 1 0x21[1] 0x31[1] x x x x x x xxx 0x03[1] vil1 drive low level, channel 1 0x23[1] 0x33[1] x x x x x x xxx 0x06[1] vch1 ref clamp high level, channel 1 0x26[1] 0x36[1] x x x 0 x x xxx ppmu clamp high level, channel 1 0x52[1] 0x6a[1] x x x 1 x x xxx 0x07[1] vcl1 ref clamp low level, channel 1 0x27[1] 0x37[1] x x x 0 x x xxx ppmu clamp low level, channel 1 0x53[1] 0x6b[1] x x x 1 x x xxx 0x0a[1] ppmu1 ppmu vin fv level, channel 1 0x2a[1] 0x3a[1] x x x x x 0 xxx ppmu vin fi range a level, channel 1 0x54[1] 0x6c[1] x x x x x 1 111 ppmu vin fi range b level, channel 1 0x55[1] 0x6c[1] x x x x x 1 110 ppmu vin fi range c level, channel 1 0x56[1] 0x6c[1] x x x x x 1 101 ppmu vin fi range d level, channel 1 0x57[1] 0x6c[1] x x x x x 1 100 ppmu vin fi range e level, channel 1 0x58[1] 0x6c[1] x x x x x 1 0xx
adate318 rev. 0 | page 67 of 80 spi address (channel) dac name functional (dac usage) description m- register c- register vhh_ enable 0x18[0] dmc_ enable 0x1c[0] load_ enablex 0x19[5] ppmu_ powerx 0x1a[15] ppmu_ meas_ vix 0x1a[5] ppmu_force _vix 0x1a[4] ppmu_ rangex (0x1a[3:1]) 0x0e[0] spare spare level 0x2e[0] 0x3e[1] x x x x x x xxx dac transfer functions table 21. detailed dac code to voltage level transfer functions levels programmable dac range 1 , 0x0000 to 0xffff dac-to-level and level-to-dac transfer functions vihx, vilx, vitx/vcomx, volx, vohx, vchx, vclx, ovdhx, ovdlx ?2.5 v to +7.5 v v out = 2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) + v dutgnd dac = [v out ? v dutgnd + 0.5 (vref ? vrefgnd)] [(2 16 )/(2 (vref ? vrefgnd))] vhh ?3.0 v to +17.0 v v out = 4 (vref ? vrefgnd) (dac/2 16 ) ? 0.6 (vref ? vrefgnd) + v dutgnd dac = [v out ? v dutgnd + 0.6 (vref ? vrefgnd)] [2 16 /(4 (vref ? vrefgnd))] iohx, iolx ?12.5 ma to +37.5 ma i out = [2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd)] (25 ma/5) dac = [(i out (5/25 ma)) + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] ppmu_vinx (fv) ?2.5 v to +7.5 v v out = 2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) + v dutgnd dac = [v out ? v dutgnd + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] ppmu_vinx (fi, range a) ?80 ma to +80 ma i out = [2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) ? 2.5] (80 ma/5) dac = [(i out (5/80 ma)) + 2.5 + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] ppmu_vinx (fi, range b) ?2 ma to +2 ma i out = [2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) ? 2.5] (2 ma/5) dac = [(i out (5/2 ma)) + 2.5 + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] ppmu_vinx (fi, range c) ?200 a to +200 a i out = [2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) ? 2.5] (200 a/5) dac = [(i out (5/200 a)) + 2.5 + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] ppmu_vinx (fi, range d) ?20 a to +20 a i out = [2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) ? 2.5] (20 a/5) dac = [(i out (5/20 a)) + 2.5 + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] ppmu_vinx (fi, range e) ?4 a to +4 a i out = [2 (vref ? vrefgnd) (dac/2 16 ) ? 0.5 (vref ? vrefgnd) ? 2.5] (4 a/5) dac = [(i out (5/4 a)) + 2.5 + 0.5 (vref ? vrefgnd)] [2 16 /(2 (vref ? vrefgnd))] 1 programmable ranges include the margin outs ide the specified performance range, allowing for offset and gain calibration. table 22. load transfer functions load level transfer functions notes iolx violx/( vref ? vrefgnd) 25 ma violx an d viohx dac levels are not referenced to v dutgnd . iohx viohx/( vref ? vrefgnd) 25 ma table 23. ppmu transfer functions ppmu mode transfer functions 1 uncalibrated ppmu_vin dac settings to achieve specified ppmu range fv vout = ppmu_vinx ?2.0 v < ppmu_vinx < +6.5 v mv vppmu_measx = vdutx (internal sense path) n/a mv vppmu_measx = vppmu_sx (external sense path) n/a fi iout = [ppmu_vinx ? (vref ? vrefgnd)/2]/(5 rppmu) 0.0 v < ppmu_vinx < 5.0 v mi vppmu_measx = [vref ? vrefgnd)/2] + (5 iout rppmu) + v dutgnd n/a 1 rppmu = 12.5 for range a, 500 for range b, 5.0 k for range c, 50 k for range d, and 250 k for range e. table 24. vhh transfer functions vhh mode transfer functions vhh hvout = 2 [vhh + (vref ? vrefgnd )/5] + v dutgnd vil hvout = vil 0 + v dutgnd vih hvout = vih 0 + v dutgnd
adate318 rev. 0 | page 68 of 80 gain and offset correction each dac within the adate318 has independent gain (m) and offset (c) correction registers that allow digital trim of gain and offset errors. dacs that are shared between functions or levels are provided with per-level or per-function gain and offset correction registers, as appropriate. these registers provide the ability to calibrate out errors in the complete signal chain, which includes error in pin electronics function as well as the dacs. all m- and c-registers are volatile and must be loaded after power-on as part of a calibration cycle if values other than the defaults are required. the gain and offset correction function can be bypassed by clearing the dac_cal_enable bit in the spi dac contol register (spi addr 0x11[0]; see figure 116). this bypass mode is available on a per-chip basis only; that is, it is not possible to bypass calibration for a subset of the dacs. the calibration function, when enabled, adjusts the numerical data sent to each dac according to the following equation: ?? 1 1 2 2 2 1 ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? n n cx m x where: x 2 = the data-word loaded into the dac and returned by an spi read operation. x 1 = the 16-bit data-word written to the dac spi input register. m = the code in the respective dac gain register (default code = 0xffff = 2 n ? 1). c = the code in the respective dac offset register (default code = 0x8000 = 2 n?1 ). n = the dac resolution ( n = 16). from this equation, it can be seen that the gain applied to the x 1 value is always less than or equal to 1.0, with the effect that a dacs output voltage can only be made smaller. to compensate for this numerically imposed limitation, the adate318s signal paths are designed to have gain guaranteed to be greater than 1.0 when the default m values (0xffff) are applied. this guarantees that proper gain calibration is always possible. note also that the value of c is expressed in raw dac lsbs; that is, it is calculated without considering the effect of the m-register. when enabled, the calibration function applies the above operation to the x 2 register(s) only after a spi write to the respective x 1 register(s). the x 2 registers are not updated after writes to either the m- or c-register. in the case of a dual channel write to the dac, two respective x 2 registers are sequentially updated using the appropriate m and c values. x 2 registers each dac has associated with it a single x 2 register. there is no provision for storing separate x 2 values for dacs shared between functions or ranges. thus, new data must be written to any shared dac after a mode or range change is performed, even if the old and new dac data is identical. the adate318 provides separate m- and c-registers for all ranges and modes so that the new x 2 value is calculated correctly following the new data write, provided the desired m and c values are stored in advance. the sequence of operations is critical in that the mode or range change must be performed prior to writing the new dac data, and both m and c values must be present before the new dac data is written. the m and/or c value can be written either before or after a mode or range change but must be written prior to the dac data to have the intended effect. sample calculations of m and c because the adate318s on-chip dacs have a theoretical output range that exceeds the operating capabilities of the remainder of its signal channels, calibration points must be chosen to be within the normal operating span. subject to this constraint, calibration is straightforward. one of the keys to understanding the calibration method is to recognize that the intrinsic dac offset is defined by its output when the input code is 0x0000. this is quite different from the case of the analog signal paths, where a 0 v level occurs when the dac code is programmed to near quarter-scale. as a first example, consider the calibration of a drive high level with a theoretical output span of ?2.5 v to ? 7.5 v, a convenient ? 10.0 v span in which dac quarter-scale corresponds to precisely 0.0 v out. the adate318 drivers do not of course support this full span, but it is a useful choice for illustration of the calibration methodology. 1. set the channel to drive high and program the vil and vit dacs for roughly ?1.0 v outputs (code 0x2700, not critical). program the vih dac to quarter-scale (0x4000) and measure output voltage v 1 ; then program the dac to three-quarter-scale (0xc000) and measure output voltage v 2 . note that v 1 and v 2 should be measured with respect to dutgnd. 2. calculate ?? 12 2__ vvfsrdac actual ?? ? where ( v 2 ? v 1 ) represents half the full-scale span. 3. calculate the extrapolated dac voltage at code 0x0000. ? ? ? ? ? ? ?? 4 __ 10 fsrdac actual vv 4. calculate ? ? 768,32 __ 12 vv lsbdac actual ? ? 5. calculate ?? 1536,65 5 12 ? ? ? ? ? ? ? ? ? ? vv m 6. calculate the offset from the ideal ?2.5 v. ? ? 0 5.2 v offset ? ? ?
adate318 rev. 0 | page 69 of 80 7. calculate ? ? ? ? ? ? ? ? ?? lsbdac actual offset c __ 768,32 8. calculate volts ? ? ? ? ? ? ? ? ? ? ? 12 5 __ __ _ vv lsbdac actual lsbdacncalibratio post the above procedure places the dacs theoretical 0x0000 output at ?2.5 v and its theoretical 0xffff output at ? 7.49985 v (1 lsb below +7.5 v). the useful range extends from below 0x199a (?1.5 v) to above 0xe666 (+6.5 v), a span of at least 52,428 actual dac codes. an alternative calibration approach can be used to map all 2 16 dac codes onto the parts specified output range by mapping the zero-code to ?1.5 v and the full-scale code to +6.5 v. 1. repeat step 1 to step 4 above. 2. calculate ?? 535,65 4 12 ? ? ? vv m 3. calculate the offset from the desired ?1.5 v. ? ? 0 5.1 v offset ? ? ? 4. calculate dac ? ? ? ? ? ? ? ? ?? lsbdac actual offset c __ 768,32 5. calculate 536,65 8 __ _ ? lsbdacncalibratio post volts although this second approach gives an apparent 16 bits of resolution covering the full signal range, it must be kept in mind that this is achieved purely by mathematical alteration of the dac data. the dacs internal lsb step size is not changed. in this example, the number of internal dac codes used to cover the signal span remains roughly 52,428 even though the number of user codes has increased to 65,536. a consequence of this is that apparent dnl errors are increased as more input codes are mapped onto the same number of dac codes. while the second calibration method is included here as an example of what is possible, its use can provide a false sense of improved accuracy and it is therefore not recommended.
adate318 rev. 0 | page 70 of 80 power supply, grounding, and decoupling strategy the adate318 product is internally divided into a digital core and an analog core. the vcc and dgnd pins provide power and ground, respectively, for the digital core, which includes the spi and all digital calibration functions. dgnd is the logic ground reference for the vcc supply, and vcc should be adequately bypassed to dgnd with low esr bypass capacitors. to reduce transient digital switching noise coupling from the vcc and dgnd pins to the analog core, dgnd should be connected to a dedicated ground domain that is separate from the analog ground domains. if the application permits, the dgnd should share digital ground domain with the system fpga or asic that interfaces with the adate318 spi. all cmos inputs and outputs are referenced between vcc and dgnd, and their valid levels should be guaranteed relative to these. the analog core of the product includes all analog ate functional blocks such as dacs, driver, comparator, load, ppmu, vhh driver, and so on. the vplus, vdd, and vss supplies provide power for the analog core. the agnd and pgnd are analog ground and analog power ground references, respectively. pgnd is generally more noisy with analog switching transients, and it may also have large static dc currents. the agnd is generally more quiet and has relatively small static dc currents. ideally, these ground domains should be separated, but it is not necessary. they can be connected together outside the chip to a shared analog ground plane. vdd and vss should be adequately bypassed to the pgnd ground domain. both pgnd and agnd (whether separated or shared) should be kept separate from the dgnd ground plane as discussed above. the vplus supply pin has the sole purpose to provide high voltage power for the vhh drive capability (hvout pin). if the vhh drive capability is used, the vplus supply must be provided as specified. if the vhh drive capability is not used, the vplus supply can be connected directly to the vdd supply domain to save power. the adate318 also has a dutgnd input pin that can be used to sense the remote dut ground potential. all dac functions (with the exception of vioh and viol active load currents and vpmu when in ppmu fi mode) are adjusted relative to this dutgnd input. further, the ppmu measure out pins (ppmu_measx) are referenced to dutgnd not agnd. this, therefore, requires the system adc to reference its inputs relative to dutgnd as well. referencing the system adc to agnd results in errors, except in the case that dutgnd is tied to agnd. for applications that do not distinguish between dut ground reference and system analog ground reference, the dutgnd pin can be connected to the same ground plane as agnd. the adate318 should have ample supply decoupling of 0.1 f on each supply pin located as close to the device as possible, ideally right up against the device. in addition, there should be one 10 f tantalum capacitor shared across each power domain. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esl), such as the common ceramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. digital lines running under the device should be avoided because these couple noise onto the device. the analog ground plane should be allowed to run under the device to avoid noise coupling. the power supply lines should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. it is essential to minimize noise on all vref lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough throughout the board. as is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process.
adate318 rev. 0 | page 71 of 80 user information and truth tables table 25. driver truth table 1 dcl control register bits (0x19) high speed inputs dcl enable addr 0x19[0] force load addr 0x19[2] force drive addr 0x19[1] force state addr 0x19[4:3] load enable addr 0x19[5] drv_vt_hiz addr 0x19 [6] rcvx datx driver 0 x x xx x x x x low leakage 1 x 1 00 x x x x vil 1 x 1 01 x x x x vih 1 x 1 10 x x x x high-z 1 x 1 11 x x x x vit 1 x 0 xx x x 0 0 vil 1 x 0 xx x x 0 1 vih 1 x 0 xx x 0 1 x high-z 1 x 0 xx x 1 1 x vit 1 x = dont care. table 26. active load truth table 1 dcl control register bits (0x19) high speed inputs dcl enable addr 0x19[0] force load addr 0x19[2] force drive addr 0x19[1] force state addr 0x19[4:3] load enable addr 0x19[5] drv_vt_hiz addr 0x19 [6] rcvx datx load 0 x x xx x x x x low leakage 1 1 x xx x x x x active on 1 0 x xx 0 x x x low leakage 1 0 x xx 1 x 0 x active off 1 0 x xx 1 0 1 x active on 1 0 x xx 1 1 1 x active off 1 x = dont care. table 27. vhh and vih/vil driver truth table 1 vhh_enable addr 0x18[0] ch0 rcv (rcv0) ch0 dat (dat0) output of vhh driver 1 0 0 vil (channel 0, vil dac) 1 0 1 vih (channel 0, vih dac) 1 1 x vhh 0 x x disabled (hvout pin set to 0.0 v, approximately 50 impedance) 1 x = dont care. table 28. comparator truth table dmc enable addr 0x1c[0] cmph0 cmpl0 cmph1 cmpl1 0 normal window compare mode logic high: voh0 < vdut0 logic low: voh0 > vdut0 normal window compare mode logic high: vol0 < vdut0 logic low: vol0 > vdut0 normal window compare mode logic high: voh1 < vdut1 logic low: voh1 > vdut1 normal window compare mode logic high: vol1 < vdut1 logic low: vol1 > vdut1 1 differential compare mode logic high: voh0 < vdut0 C vdut1 logic low: voh0 > vdut0 C vdut1 differential compare mode logic high: vol0 < vdut0 ? vdut1 logic low: vol0 > vdut0 ? vdut1 normal window compare mode logic high: voh1 < vdut1 logic low: voh1 > vdut1 normal window compare mode logic high: vol1 < vdut1 logic low: vol1 > vdut1
adate318 rev. 0 | page 72 of 80 alarm functions the adate318 contains per-channel overvoltage detectors (ovd), ppmu voltage/current clamps, and a per-chip thermal alarm to detect and signal fault conditions. the status of these circuits may be interrogated via the spi by reading the alarm state register (spi addr 0x1e; see figure 124 ). this read-only register is cleared by a read operation. in addition, the fault conditions are combined in the fault alarm logic (see figure 137 ) and drive the open drain alarm pin to signal that a fault has occurred. the various alarm circuits are controlled through the alarm mask register (addr 0x1d; see figure 123 ). in the default state, the thermal alarm is enabled, and both the overvoltage alarm and the ppmu clamp alarms are masked off. the only function of the alarm circuits is to detect and signal the presence of a fault. the only actions taken upon detection of a fault are setting of the appropriate register bit and activating the alarm pin. ppmu external capacitors table 29. ppmu external compensation and feedforward capacitors external components location 220 pf between ffcapb0 and ffcapa0 220 pf between ffcapb1 and ffcapa1 1000 pf between agnd and scap0 1000 pf between agnd and scap1 table 30. other external components external components location 10 k alarm pull-up to vcc 1 k busy pull-up to vcc temperature sensor table 31. temperature output 0 k 0.00 v 300 k 3.00 v t kelvin 0.00 v + (t kelvin ) 10 mv/k
adate318 rev. 0 | page 73 of 80 default test conditions table 32. name default test condition vihx dac levels 2.0 v vitx/vcomx dac levels 1.0 v vilx dac levels 0.0 v vohx dac levels 6.5 v volx dac levels ?1.5 v vchx dac levels 7.5 v vclxdac levels ?2.5 v viohxdac levels 0.0 ma violx dac levels 0.0 ma ppmu_vinx dac levels 0.0 v vhh dac level 13.0 v ovdh dac levels 7.0 v ovdl dac levels ?2.0 v dac_control 0x0000: dac calibration disabled, dac load mode is immediate vhh_control 0x0000: hvout (vhh) disabled dcl_control 0x0001: dcl enabled, load disabled, high-z for rcvx = 1, force drive = 0 (to vil state) ppmu_control 0x0000: ppmu disabled, ppmu range e, force-v 1 /measure-v 2 , input to v dutgnd , internal sense path, clamps disabled, external pp mu_s open, ppmu_power_x off ppmu_meas_control 0x0000: ppmu_measx high-z comparator_control 0x0000: normal window compar ator mode, comparator hysteresis disabled alarm_mask 0x0045: disable alarm functions pre_emphasis_control 0x0000: disable driver clc, differenti al comparator clc, and normal window comparator clc calibration m-coefficients 1.0 (0xffff) calibration c-coefficients 0.0 (0x8000) datx, rcvx inputs logic low dutx pins unterminated cmphx, cmplx outputs unterminated v dutgnd 0.0 v 1 force-v indicates force voltage. 2 measure-v indicates measure voltage.
adate318 rev. 0 | page 74 of 80 detailed functional block diagrams 09530-023 dac vchx dac vit/vccmx dac vclx dac vihx dac vilx drv addr 0x01, chx addr 0x06, chx addr 0x07, chx addr 0x02, chx addr 0x03, chx datx dutx 50 ? term 1 0 1 0 0 (ideal clamp diodes) high-z drv_rcv_mode (see the driver logic diagram) drv_low_leak (see the driver logic diagram) drv_rcv_sw (see the driver logic diagram) pmu clamp levels shared with high s peed dcl clamps figure 127. driver block diagram 09530-024 dcl_enable addr 0x19[0] force_drv addr 0x19[1] force_state[1] addr 0x19[4] force_state[0] addr 0x19[3] drv_vt_hiz addr 0x19[6] drv_low_leak drv_rcv_mode (see the driver block diagram) drv_rcv_sw (see the driver block diagram) rcvx drv_low_leak = dcl_enable drv_rcv_mode = drive_vt_hiz + force_drv force_state[0] drv_rcv_sw = force_drv force_state[1] + force_drv rcvx figure 128. driver logic diagram
adate318 rev. 0 | page 75 of 80 v cm v dm dat 1.30v 1.10v dat v cm = 1.20v v dm = 200mv v cm v dm rcv 1.25v 0.95v rcv dat dat rcv rcv v cm = 1.10v v dm = 300mv typical input waveforms to driver, load, and vhh 0.0v v cm 3.3v 200mv v dm 1.0v 100 ? 100 ? adate318 09530-025 figure 129. driver input stage diagram dac viol addr 0x09 active load dac vit/vcom addr 0x2 dac vioh addr 0x08 from driver 50? dutx load_connect (see the active load logic diagram) load_pwr_down (see the active load logic diagram) 09530-026 figure 130. active load block diagram dcl_enable addr 0x19[0] force_load addr 0x19[2] load_enable addr 0x19[5] drv_vt_hiz rcvn load_pwr_down (see the active load block diagram) load_connect (see the a ctive load block diagram) addr 0x19[6] load_connect = dcl_enable (force_load + rcvn drv_vt_hiz load_enable) load_pwr_down = dcl_enable + force_load load_enable 09530-027 figure 131. active load logic diagram
adate318 rev. 0 | page 76 of 80 09530-028 dac vhh vhh (note 1) vhh driver vl/vh driver vil (note 2) hvout 50? 50? <5 ? vih (note 2) dac vil dac vih vdutgnd dat0 rcv0 notes 1. vhh = 2 (dac vhh + (v ref ? v refgnd )/5 + v dutgnd ) ? v dutgnd 2. vil = dac vil + v dutgnd ; vih = dac vih + v dutgnd vhh_en figure 132. vhh and vil/vih driver block diagram 09530-029 hvout rcv0 l h h l l don?t care dat0 l h l h l h l h don?t care don?t care vhh_enable addr 0x18[0] dac vih dac vhh dac vil 0.0v figure 133. vhh and vil/vih waveform diagram
adate318 rev. 0 | page 77 of 80 09530-030 dac voh0 dac voh0 dac vol0 differential comparator on channel 0 only to dut1 addr 0x04 dac vol0 dmc_enable addr 0x1c[0] addr 0x05 comph 0 1 0 1 compl compl comph dut0 figure 134. comparator block diagram 09530-031 50? vttc 0.5 v v tt_ext v ttcx 50? 50? 50? 50? 250mv vttc vhi = vttc ? 25mv vlo = vttc ? 275mv 50? output waveform adate318 cmp cmp 10ma figure 135. comparator output stage diagram
adate318 rev. 0 | page 78 of 80 09530-032 f-amp pmu_sx dutx ppmu_sx ppmu_measx (re l ative to vdutgnd) ppmu_cmphx ppmu_cmplx 0 1 2 3 dac vch vdutgnd 2.5v + vdutgnd dac vcl addr 0x06, chx pmu clamp levels shared with high speed dcl clamps addr 0x07, chx ppmu_force_e_vi_x ppmu_meas_vi_x addr 0x1a[4], chx ppmu_meas_sel_x addr 0x1b[1], chx addr 0x1a[5], chx ppmu_meas_enable_x addr 0x1b[0], chx addr 0x0a, chx ppmu_input_sel_x addr 0x1a[7:6], chx ppmu_range_x addr 0x1a[3:1], chx vref/2 + vdutgnd a v = 5.0 a v = 1.0 ppmu_clamp_enable_x addr 0x1a[9], chx r ppmu ppmu_sense_path_x addr 0x1a[8], chx ppmu_enable_x addr 0x1a[0], chx ppmu_s_enable_x addr 0x1a[ 11], chx dac ppmu addr 0x04, chx voh x 1.2k f-amp i-amp current voltage 1 0 1 ch0: therm out ch1: therm gnd addr 0x05, chx vol x range 40ma 1ma 100a 10a 2a r ppmu 12.5 ? 500 ? 5k? 50k ? 250k ? ppmu_enable_x ppmu_power_x addr 0x1a[0], chx addr 0x1a[15], chx 0 x ppmu is powered down. 1 0 ppmu is in full-power standby mode but not yet enabled to force v/force i. use this mode for fast internal settling of levels prior to enabling active mode to minimize ppmu glitching. ppmu go/no-go comparator dac levels are shared with the high speed pe comparator. when ppmu is not in active mode, ppmu go/no-go comparators are not used and their outputs are forced to static low. 1 1 ppmu is in full-power active mode. figure 136. ppmu block diagram
adate318 rev. 0 | page 79 of 80 dac ovdh dac ovdl addr 0x0c, ch0 addr 0x0d, ch0 ovd_alarm_mask_x addr 0x1d[0], chx therm_alarm_mask addr 0x1d[3], ch0 therm_threshold addr 0x1d[6:4], ch0 ppmu_alarm_mask_x addr 0x1d[2], chx temperature sensor (10mv/k) note: dedicated ppmu clamp indicators are provided for each channel. only one channel is shown here. note: dedicated overvoltage window comparators are provided for each channel. only one channel is shown here. the dac ovdx , levels are shared between channels. from ppmux clamp indicator v cc v cc dq q reset by reading from spi alarm state register addr 0x1e, chx alarm dutx therm (10mv/k) 09530-033 figure 137. fault alarm block diagram
adate318 rev. 0 | page 80 of 80 outline dimensions 9.75 bsc sq 10.00 bsc sq 1 21 63 43 22 42 84 64 0.60 0.50 0.40 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 8.00 ref 6.85 6.75 sq 6.65 0.40 bsc 0.20 ref 12 max 0.05 max 0.01 nom seating plane 0.70 0.60 0.50 top view pin 1 indicator 0.90 0.85 0.80 0.70 0.65 0.60 bottom view compliant to jedec standards mo-262-vhhe. notes: 1. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 2. tiebars must be soldered to the board. 08-18-2010-a 0.93 0.83 0.73 0.35 (see note 2) 0.25 (see note 2) exposed pad (see note 1) figure 138. 84-lead lead frame chip scale package [lfcsp_vq] 10 mm 10 mm body, very thin quad (cp-84-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADATE318BCPZ t j = +25c to +70c 84-lead lfcsp_vq with exposed pad cp-84-2 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09530-0-4/11(0)

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